NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 74

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Table 2-21. General Purpose I/O Signals (Sheet 3 of 3)
2.23
Table 2-22. Power and Ground Signals (Sheet 1 of 3)
74
1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI,
2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven
NOTES:
(Desktop Only)
(Desktop Only)
(Desktop and
GPIO[15:12]
Power and Ground
Mobile Only)
but not both.
high into powered-down planes. Some ICH7 GPIOs may be connected to pins on devices that exist in the core
well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button
Override event will result in the Intel ICH7 driving a pin to a logic 1 to another device that is powered down.
GPIO[10:8]
GPIO[7:6]
GPIO[5:2]
(Desktop and
Name
Mobile Only)
GPIO19
GPIO18
GPIO17
GPIO16
GPIO11
Vcc1_5_A
Vcc1_5_B
GPIO1
GPIO0
Vcc1_05
Vcc3_3
Name
V5REF
1,2
Type
These pins provide the 3.3 V supply for core well I/O buffers (22pins). This
power may be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.05 V supply for core well logic (20 pins). This power
may be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.5 V supply for Logic and I/O (30 pins). This power may
be shut off in S3, S4, S5 or G3 states.
These pins provide the 1.5 V supply for Logic and I/O (53 pins). This power may
be shut off in S3, S4, S5 or G3 states.
These pins provide the reference for 5 V tolerance on core well inputs (2 pins).
This power may be shut off in S3, S4, S5 or G3 states.
I/OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Tolerance
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
5 V
5 V
Resume
Resume
Resume
Power
Well
Core
Core
Core
Core
Core
Core
Core
Core
Description
(Desktop)
Mobile) /
Default
(Mobile/
Native
Native
Ultra
GPO
GPO
GPI
GPO
GPI
GPI
GPI
GPI
GPI
GPI
Multiplexed with SATA1GP.
Mobile/Ultra Mobile Only: GPIO is
not implemented and is used
instead as STP_PCI#.
Desktop Only: Unmultiplexed.
Multiplexed with GNT5#.
Mobile/Ultra Mobile Only:
Natively used as DPRSLPVR.
Desktop Only: Unmultiplexed.
Unmultiplexed.
Multiplexed with SMBALERT#
Unmultiplexed.
Unmultiplexed.
Multiplexed with PIRQ[H:E]#.
Multiplexed with REQ5#.
Mobile/Ultra Mobile Only:
Multiplexed with BM_BUSY#.
Desktop Only: Unmultiplexed
Intel
®
Description
ICH7 Family Datasheet
Signal Description