NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 729

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Intel® High Definition Audio Controller Registers (D27:F0)
Table 19-2. Intel
Intel
®
ICH7 Family Datasheet
(Intel
HDBAR +
8Ch–8Dh
ACh–ADh
5Ah–5Bh
88h–8Bh
98h–9Bh
A0h–A2h
A4h–A7h
A8h–ABh
B0h–B1h
BCh–BFh
C0h–C2h
58h–59h
60h–63h
64h–67h
68h–69h
70h–73h
74h–77h
84h–87h
90h–91h
92h–93h
9Ch–9Fh
AEh–AFh
B8–BBh
80–82h
B2–B3h
8Eh–8F
Offset
5Dh
5Ch
5Eh
83h
A3h
®
®
High Definition Audio PCI Register Address Map
High Definition Audio D27:F0) (Sheet 2 of 4)
ISD0FIFOW
ISD1FIFOW
Mnemonic
ISD0FIFOS
ISD1FIFOS
ISD0BDPU
ISD1BDPU
ISD0BDPL
ISD1BDPL
RIRBSIZE
DPUBASE
ISD0LPIB
ISD1LPIB
RINTCNT
DPLBASE
ISD0FMT
ISD1FMT
RIRBSTS
ISD0STS
ISD0CBL
ISD1CTL
ISD1STS
ISD1CBL
RIRBCTL
ISD0CTL
ISD2CTL
RIRBWP
ISD0LVI
ISD1LVI
IRS
IC
IR
RIRB Write Pointer
Response Interrupt Count
RIRB Control
RIRB Status
RIRB Size
Immediate Command
Immediate Response
Immediate Command Status
DMA Position Lower Base Address
DMA Position Upper Base Address
Input Stream Descriptor 0 (ISD0)
Control
ISD0 Status
ISD0 Link Position in Buffer
ISD0 Cyclic Buffer Length
ISD0 Last Valid Index
ISD0 FIFO Watermark
ISD0 FIFO Size
ISD0 Format
ISD0 Buffer Descriptor List Pointer-
Lower Base Address
ISD0 Buffer Description List Pointer-
Upper Base Address
Input Stream Descriptor 1(ISD01)
Control
ISD1 Status
ISD1 Link Position in Buffer
ISD1 Cyclic Buffer Length
ISD1 Last Valid Index
ISD1 FIFO Watermark
ISD1 FIFO Size
ISD1 Format
ISD1 Buffer Descriptor List Pointer-
Lower Base Address
ISD1 Buffer Description List Pointer-
Upper Base Address
Input Stream Descriptor 2 (ISD2)
Control
Register Name
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
040000h
040000h
040000h
Default
0000h
0000h
0000h
0000h
0004h
0077h
0000h
0000h
0004h
0077h
0000h
00h
00h
42h
00h
00h
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
Access
R/W, R/
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WC
RO
RO
RO
RO
RO
RO
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