NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 643

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Intel
®
ICH7 Family Datasheet
4:3
Bit
16
15
14
13
12
11
10
9
8
7
6
5
AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and
maintains context across power states (except G3). The bit has no hardware function.
It is used by software in conjunction with the MD3 bit to coordinate the entry of the two
codecs into D3 state.
NOTE: This bit is not affected by D3
Read Completion Status (RCS) — R/WC. This bit indicates the status of codec read
completions.
0 = A codec read completes normally.
1 = A codec read results in a time-out. The bit remains set until being cleared by
NOTE: This bit is not affected by D3
Bit 3 of Slot 12 — RO. Display bit 3 of the most recent slot 12.
Bit 2 of Slot 12 — RO. Display bit 2 of the most recent slot 12.
Bit 1 of slot 12 — RO. Display bit 1 of the most recent slot 12.
ACZ_SDIN1 Resume Interrupt (S1R1) — R/WC. This bit indicates that a resume
event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.
0 = Resume event did Not occur
1 = Resume event occurred.
NOTE: This bit is not affected by D3
ACZ_SDIN1 Resume Interrupt (S1R1) — R/WC. This bit indicates that a resume
event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.
0 = Resume event did Not occur
1 = Resume event occurred.
NOTE: This bit is not affected by D3
ACZ_SDIN0 Codec Ready (S0CR) — RO. Reflects the state of the codec ready bit in
ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software
must check this bit before starting the bus masters. Once the codec is “ready”, it must
not go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
ACZ_SDIN0 Codec Ready (S0CR) — RO. Reflects the state of the codec ready bit in
ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software
must check this bit before starting the bus masters. Once the codec is “ready”, it must
not go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Microphone In Interrupt (MINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the Mic in channel interrupts status bits has been set.
PCM Out Interrupt (POINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM out channel interrupts status bits has been set.
PCM In Interrupt (PIINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM in channel interrupts status bits has been set.
Reserved
software writing a 1 to the bit location.
HOT
HOT
HOT
HOT
Description
to D0 Reset.
to D0 Reset.
to D0 Reset.
to D0 Reset.
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