NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 66

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Table 2-12. Power Management Interface Signals (Sheet 3 of 3)
2.13
Table 2-13. Processor Interface Signals (Sheet 1 of 3)
66
Processor Interface
(Desktop Only)
(Desktop Only)
(Desktop Only)
(Desktop Only)
Mobile Only) /
Mobile Only) /
Mobile Only) /
Mobile Only) /
(Mobile/Ultra
(Mobile/Ultra
(Mobile/Ultra
(Mobile/Ultra
STP_CPU#
DPRSLPVR
CPUSLP#
BATLOW#
DPRSTP#
A20M#
FERR#
Name
GPIO20
GPIO16
Name
TP0
TP1
Type
O
O
I
Type
O
O
O
I
Mask A20: A20M# will go active based on either setting the appropriate
bit in the Port 92h register, or based on the A20GATE input being active.
CPU Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that
time, no snoops occur. The Intel
signal when going to the S1 state. (Desktop Only)
Reserved. (Mobile/Ultra Mobile Only)
Numeric Coprocessor Error: This signal is tied to the coprocessor error
signal on the processor. FERR# is only used if the ICH7 coprocessor error
reporting function is enabled in the OIC.CEN register (Chipset Config
Registers:Offset 31FFh: bit 1). If FERR# is asserted, the ICH7 generates
an internal IRQ13 to its interrupt controller unit. It is also used to gate the
IGNNE# signal to ensure that IGNNE# is not asserted to the processor
unless FERR# is active. FERR# requires an external weak pull-up to
ensure a high level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the processor
Stop CPU Clock: This signal is an output to the external clock
generator for it to turn off the processor clock. It is used to support
the C3 state. If this functionality is not needed, this signal can be
configured as a GPIO.
NOTE: Refered to as STPCPU# on Ultra Mobile.
Battery Low: This signal is an input from battery to indicate that
there is insufficient power to boot the system. Assertion will prevent
wake from S3–S5 state. This signal can also be enabled to cause an
SMI# when asserted.
Deeper Sleep - Voltage Regulator: This signal is used to lower the
voltage of VRM during the C4 state. When the signal is high, the
voltage regulator outputs the lower “Deeper Sleep” voltage. When low
(default), the voltage regulator outputs the higher “Normal” voltage.
Deeper Stop: This is a copy of the DPRSLPVR and it is active low.
of pending interrupt events. This functionality is independent of
the OIC register bit setting.
Description
®
Description
ICH7 can optionally assert the CPUSLP#
Intel
®
ICH7 Family Datasheet
Signal Description