NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 565

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
13.2.2.1
Intel
®
ICH7 Family Datasheet
implemented in the core power well. Unless otherwise noted, the core well registers are
reset by the assertion of any of the following:
The second set at offsets MEM_BASE + 60h to the end of the implemented register
space are implemented in the Suspend power well. Unless otherwise noted, the
suspend well registers are reset by the assertion of either of the following:
USB2.0_CMD—USB 2.0 Command Register
Offset:
Default Value:
31:24
23:16
• Core well hardware reset
• HCRESET
• D3-to-D0 reset
• Suspend well hardware reset
• HCRESET
15:8
11:8
Bit
7
Reserved. These bits are reserved and should be set to 0 when writing this register.
Interrupt Threshold Control — R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
Reserved. These bits are reserved and should be set to 0 when writing this register.
Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host
controller does not support this optional feature.
Light Host Controller Reset — RO. Hardwired to 0. The Intel
this optional reset.
Value
00h
01h
02h
04h
08h
10h
20h
40h
MEM_BASE + 20–23h
00080000h
8 micro-frames (default, equates to 1 ms)
Maximum Interrupt Interval
16 micro-frames (2 ms)
32 micro-frames (4 ms)
64 micro-frames (8 ms)
2 micro-frames
4 micro-frames
1 micro-frame
Reserved
Description
Attribute:
Size:
®
R/W, RO
32 bits
ICH7 does not implement
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