NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 723

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.39
19.1.40
19.1.41
Intel
®
ICH7 Family Datasheet
PVCCTL — Port VC Control Register
(Intel
Address Offset: 10Ch–10Dh
Default Value:
PVCSTS—Port VC Status Register
(Intel
Address Offset: 10Eh-10Fh
Default Value:
VC0CAP—VC0 Resource Capability Register
(Intel
Address Offset: 110h–113h
Default Value:
31:24
22:16
15:4
15:1
13:8
3:1
7:0
Bit
Bit
Bit
23
15
14
0
0
Reserved.
VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However,
these bits are not applicable since the Intel
in the Low Priority Extended VC Count bits in the PVCCAP1 register.
Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not
present.
Reserved.
VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not
present.
Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
Reserved.
Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
Reserved.
Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
®
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
0000h
0000h
00000000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
High Definition Audio controller reports a 0
RO
16 bits
RO
16 bits
RO
32 bits
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