NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 143

• Manufacturer Part Number: NH82801GHM S L8YR
• Manufacturer: Intel

Specifications of NH82801GHM S L8YR

• Lead Free Status / RoHS Status: Compliant

Functional Description
Table 5-18. Interrupt Message Data Format
5.11
Note:
5.11.1
Intel
®
ICH7 Family Datasheet
Start Frame
Serial Interrupt (D31:F0)
The ICH7 supports a serial IRQ scheme. This allows a single signal to be used to report
interrupt requests. The signal used to transmit this information is shared between the
host, the ICH7, and all peripherals that support serial interrupts. The signal line,
SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is
used by all PCI signals. This means that if a device has driven SERIRQ low, it will first
drive it high synchronous to PCI clock and release it the following PCI clock. The serial
IRQ protocol defines this sustained tri-state signaling in the following fashion:
The ICH7 supports a message for 21 serial interrupts. These represent the 15 ISA
interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and
IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts
(20–23).
When the IDE controller is enabled or the SATA controller (Desktop and Mobile Only) is
configured for legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA
legacy interrupts, which cannot be shared, i.e. through the Serial Interrupt pin. If
IRQ14 and IRQ15 are shared with Serial Interrupt pin then abnormal system behavior
may occur. For example, IRQ14/15 may not be detected by ICH7's interrupt controller.
The serial IRQ protocol has two modes of operation which affect the start frame. These
two modes are: Continuous, where the ICH7 is solely responsible for generating the
start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the
start frame.
• S – Sample Phase. Signal driven low
• R
• T
31:16
13:12
10:8
7:0
Bit
15
14
11
–
–
Turn-around Phase. Signal released
Recovery Phase. Signal driven high
Will always be 0000h.
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O
Redirection Table for that interrupt.
Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit
is always 1.
Will always be 00
Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the
I/O Redirection Table for that interrupt.
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection
Table for that interrupt.
000 = Fixed 100 = NMI
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Reserved
011 = Reserved 111 = ExtINT
Vector: This is the same as the corresponding bits in the I/O Redirection Table for
that interrupt.
Description
143