NH82801GHM S L8YR Intel, NH82801GHM S L8YR Datasheet - Page 408
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NH82801GHM S L8YR
Manufacturer Part Number
NH82801GHM S L8YR
Description
Manufacturer
Intel
Datasheet
1.NH82801GHM_S_L8YR.pdf
(848 pages)
Specifications of NH82801GHM S L8YR
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NOTE: Delivery Mode encoding:
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
10:8
7:0
Bit
11
Trigger Mode can be edge or level.
executing at the lowest priority among all the processors listed in the specified
destination. Trigger Mode can be edge or level.
triggered. The vector information is ignored but must be programmed to all 0’s for future
compatibility: not supported
Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is
programmed as level triggered. For proper operation this redirection table entry must be
programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the
redirection table is incorrectly set to level, the loop count will continue counting through
the redirection table addresses. Once the count for the NMI pin is reached again, the
interrupt will be sent again: not supported
INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated
as an edge triggered interrupt even if programmed as level triggered. For proper
operation this redirection table entry must be programmed to edge triggered. The INIT
delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level,
the loop count will continue counting through the redirection table addresses. Once the
count for the INIT pin is reached again, the interrupt will be sent again: not supported
as an interrupt that originated in an externally connected 8259A compatible interrupt
controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the
external controller that is expected to supply the vector. Requires the interrupt to be
programmed as edge triggered.
Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.
Lowest Priority. Deliver the signal on the INTR signal of the processor core that is
SMI (System Management Interrupt). Requires the interrupt to be programmed as edge
Reserved
NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination.
INIT. Deliver the signal to all processor cores listed in the destination by asserting the
Reserved
ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination
Destination Mode — R/W. This field determines the interpretation of the Destination
field.
0 = Physical. Destination APIC ID is identified by bits 59:56.
1 = Logical. Destinations are identified by matching bit 63:56 with the Logical
Delivery Mode — R/W. This field specifies how the APICs listed in the destination field
should act upon reception of this signal. Certain Delivery Modes will only operate as
intended when used in conjunction with a specific trigger mode. These encodings are
listed in the note below:
Vector — R/W. This field contains the interrupt vector for this interrupt. Values range
between 10h and FEh.
Destination in the Destination Format Register and Logical Destination Register in
each Local APIC.
Description
LPC Interface Bridge Registers (D31:F0)
Intel
®
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