pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 99

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Pending interrupts, enabled or disabled, can be polled using the Status registers. The CR16B core supports INT0, but the
ICU reserves INT0 so that it is not connected to any interrupt source.
Maskable Interrupt Vectors
Interrupt vector numbers are always positive and are in the range 10
tor of the enabled and pending interrupt with the highest priority. The interrupt vector 10
est priority; the vector 2F
The CR16B core performs an “Interrupt Acknowledge” bus cycle on receiving an enabled maskable interrupt request from
the ICU. During the interrupt acknowledge cycle, a byte is read from address 00 FE00
used as an index in the Dispatch Table to determine the address of the interrupt handler.
Although INT0 is not connected to any interrupt source, the IVCT register can return the value 10
ample, when the interrupt request is removed before the interrupt acknowledge cycle. The entry in the Dispatch Table should
point to a default interrupt handler that handles this error condition.
Pending Interrupts
Edge-triggered interrupts are latched by the Interrupt Status register. A pending edge-triggered interrupt is cleared by writing
a ‘1’ to the respective bit in the Edge Interrupt Clear register, IECLR0 or IECLR1.
A pending level-triggered interrupt is cleared when the interrupt source is not active; note that the interrupt should be cleared
at the device/module that drives it by clearing the event status bit.
Interrupt mask bits (IENAM register bits) and pending interrupt bits (ISTAT register bits), should be cleared to 0 only when
interrupts are disabled; i.e., when bits I and/or E in PSR register (a core register) are 0. Bits in IENAM may be set at any time.
Interrupt Priorities
The priorities of the maskable interrupts are hard-wired and thus fixed. The interrupts are named INT0 to INT31, where INT0
has the lowest priority and INT31 has the highest priority.
Power-Down Modes
Interrupt sources that may generate unexpected interrupts in Idle mode should be masked before switching to the power-
down mode.
External Interrupt Inputs
When an MIWU input is disabled, and the respective WKOxx output at the MIWU is connected to the ICU, the MIWU input
is fed directly to the ICU. In this case, the interrupt inputs are asynchronous. They are recognized by the PC87591x during
cycles in which the input setup and hold time requirements are satisfied. To use an external interrupt which is shared with
an I/O port, configure the I/O port to its alternate function (see Section 2.4 on page 54).
Interrupt Assignment
Table 16 shows the mapping of the ICU maskable interrupts to different functions. For information on mask bits and the clear
mechanism for the status bit in internal level interrupts, refer to descriptions of the module that is the interrupt source.
Number
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT
External/MIWU
External/MIWU
Source
Internal
Internal
Internal
Internal
Internal
-
16
corresponds to INT31 with the highest priority.
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Type
-
Table 16. ICU Interrupt Assignments
(Continued)
Error condition occurred (spurious interrupt)
External Interrupt EXWINT20 through the MIWU
Host I/F Keyboard/Mouse channel Output Buffer Empty
Host I/F Power Management channel 1 or channel 2 Output
Buffer Empty
High-Frequency Clock Generator
MIWU PSWUINT or WKINTD
External Interrupt EXWINT23 through the MIWU
MFT16 1 Interrupt (INT1 ORed with INT2)
99
16
to 2F
16
Details
. The IVCT register contains the interrupt vec-
16
16
corresponds to INT0 with the low-
(IVCT register). The byte read is
16
1
1
. This happens, for ex-
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Priority
Lowest