pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 329

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host Controller Interface Modules
MSWC Control Status Register 1 (MSWCTL1)
This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. The contents of
this register are preserved by V
Location: 00 FCC0
Type: Varies per bit
Bit
Name
Reset
7-6
Bit
0
1
2
3
4
5
R/W1C VHCFGA (Valid Host Configuration Address). This bit is set by a write to HCFGBAH register, as
R/W1C HSECM (Host Software Event Clear Mode). Controls the clear mode of Host Software Event Status
R/W1S HCFGLK (Host Configuration Address Lock). This bit is cleared during V
Type
R/W
RO
RO
16
HRSTOB (Host Reset Out Bit). Enables the PC87591x to generate a Host Soft reset via firmware,
using the KBSTO pin. The pin is held low (reset is active) for as long this bit 1.
0: KBRST is not forced active (default)
1: Force KBRST active
HPWRON (Host Power On). The V
0: V
1: V
LPCRSTA (LPC Reset Active). The RESET1 input is active (low).
0: RESET1 is not active (high)
1: RESET1 is active (low)
detailed in the update sequence in “Host Configuration Address Selection” on page 322. The firmware
can clear the bit by writing 1 to it. This register is used as the address of the Configuration registers
when the PC87591x is set to operate with the internal base address. Writing 0 to this bit is ignored.
This bit can be locked and made read-only by setting HCFGLK (bit 4).
0: Host Configuration Registers base address is not valid and access to this registers by the host is not
1: Host Configuration Registers base address is specified in HCFGBAH and HCFGBAL registers
WATCHDOG reset or Debugger Interface reset, but is unchanged during other reset events.
When 1 is written to this bit, it becomes read only (i.e., it cannot be cleared by the firmware) and locks
VHCFGA bit, HCFGBAH register and HCFGBAL register, preventing accidental alteration to them.
0: Allows update of the Host Configuration Registers base address (default)
1: Locks the Host Configuration Registers base address
bit in WK_STS0. This bit is cleared at V
0: Host Software Event Status bit in WK_STS0 (bit 6) toggles on host writes of 1. MSHES0 bit 6 is set
1: Host Software Event Status bit in WK_STS0 (bit 6) and MSHES0 bit 6 are both cleared by writes of
Reserved.
7
0
Reserved
enabled (default)
when WK_STS0 bit 6 changes from 0 to 1 (default).
1 to MSHES0 register
DD
DD
is off (below V
is on (above V
CC
6
0
. Bit 0 is cleared by Warm reset; other bits are reset only on V
DDON
DDON
HSECM
)
5
0
)
(Continued)
DD
HCFGLK
power detection logic indicates that V
329
CC
4
0
power-up and RESET1 events.
Description
VHCFGA
3
0
LPCRSTA
0
2
CC
CC
HPWRON
DD
Power-Up reset.
power-up,
is on.
1
-
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HRSTOB
0
-