pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 309

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host Controller Interface Modules
Shared Memory Core Override Read Protect Registers 0-2 (SMCORP0-2)
SMCORP0-2 are 16-bit registers that provide core override on the host read protection bits. For the host to be able to read
a memory location, both the Host Read Protection bit (controlled through the Shared Memory Host Access Protect Register
1 or 2) and the associated bit in SMCORP0-2 should be cleared. Each bit in this register is associated with a memory block,
as described in the bits description. Bits in these registers may be RO or RW depending on their position and the size of the
core and host boot blocks. SMCORP0-2 registers are loaded with reset values either on reset or when the value of the
SMCTA register is changed; the reset values depend on the size of the core and host boot blocks, as defined in the protec-
tion word.
Location: 00 F910
Type: R/W or RO as described in the description below
Bit
Name
Reset
Bit
Name
Reset
Bit
Name
Reset
15-0 ORPLA15-0 (Override Read Protect Low Addresses 15 through 0).
3-0
7-4
Bit
Bit
1. Use the MBTA as specified in SMCTA register, without the MBTA override in the protection word.
ORP15-2 (Override Read Protect 15 through 2).
ORP31-16 (Override Read Protect 15 through 0).
Each bit affects the host’s ability to read from one block. On the low addresses (covered by ORPLAi), the block
size is 8 Kbytes. For the other blocks it is 64 Kbytes. The block address is calculated as follows:
See Figure 102 on page 302 for a description of the block mapping. Bit 7 (ORPLA7) in SMCORP0 register is
read only.
0: Do not override the host read protect setting for the block
1: Host read for this block is disabled regardless of the setting of the respective bit in the host register
The reset values of these registers are as follows:
The following access limitations apply to the register bits:
Type
R/W CSEM3-0. Four bits that may be updated by the core and read by both the host and the core.
RO
Low address blocks, ORPLAi: from i*8K to (i+1)*8K 1
Other blocks, ORPLj: from j*64K to (j+1)*64K
Core boot blocks that cover address 00 0000
Host boot blocks not in above group and from (MBTA
All other blocks:
Core boot blocks that cover address 00 0000
Host boot blocks not in above group and ranging from (MBTA
All other blocks:
15
15
15
HSEM3-0. Four bits that may be updated by the host and read by both the host and the core.
16
, 00 F912
14
14
14
See bit description below
13
13
13
16
, 00 F914
12
12
12
16
11
11
11
See bit description below
10
10
10
(Continued)
See bit description below
ORP15-2
9
9
9
16
16
Description
309
to CR_Boot_Block_Size:
to CR_Boot_Block_Size:
ORPLA15-0
ORP 31-16
Description
8
8
8
1
Host_Boot_Block_Size) to MBTA:
7
1
7
7
1
6
6
6
Host_Boot_Block_Size) to MBTA:RO
5
5
5
See bit description below
4
4
4
3
3
3
2
2
2
Reserved
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1
1
0
1
1
0
1
RO
RW
0
0
0
0