pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 68

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

www.national.com
3.0 Power, Reset and Clocks
3.3
The PC87591x has three clock domains, as shown in Table 12.
Core Domain Clock
The core clock is sourced by the HFCG. The following section gives an overview of the clock domain.
On V
ware. See Section 4.18 on page 239.
On WATCHDOG reset (or Debugger interface reset), the HFCG is reset.
LPC Clock
The LPC interface is driven by the LCLK input. LCLK frequency can be up to 33 MHz. The clock CLKRUN signal may be
used as part of a power management scheme that slows the clock down; see “CLKRUN Functionality” on page 343.
RTC (32 KHz) Clock
The RTC clock is the reference for the generation of all other clocks in the PC87591x. The clock is enabled at V
up and is kept active while V
The RTC clock is used for time keeping in the RTC; it is also fed into the Power Management Controller (PMC), which pro-
vides the clock to other functions (such as TWD and ACM) that are active at all times (including Idle).
Clock Domain
CC
CLOCK DOMAINS
1. See Section 6.2.3 on page 356 and Section 6.2.4 on page 357.
Power-Up reset, the HFCG is set to generate a 4 MHz clock. The HFCG frequency can be modified by core firm-
Core
LPC
RTC
See Section 4.18
Up to 33 MHz
on page 239
Frequency
32 KHz
PP
is active. Keeping the RTC clock active significantly reduces the PC87591x wake-up time.
Table 12. PC87591x Clock Domains
(Continued)
Clock input or on-chip oscillator
LPC clock input
Source
HFCG
68
1
Core domain and host-core interface
RTC, HFCG, TWD, PMC, ACM
LPC bus interface
Usage
CC
Revision 1.07
power-