pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 279

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
5.0 Host Controller Interface Modules
Status Read
Both the host and the core can read the status of the KBC data buffers. Bits 2 and 4 to 7 can be written by the core. The
host processor should read address 64
information by reading/writing the HIKMST register. The format of the Status register is identical for both the host and the
core (see “Host Interface Keyboard/Mouse Status Register (HIKMST)” on page 284).
Host Data Write to Host Interface Keyboard/Mouse Channel
The data buffer has two latches; one serves as an input buffer and the other as an output buffer. When writing to address
60
register is set and bit 3 (A2) in the Status register indicates to the core which address (command or data) was written to.
When writing to address 60
A2=1), bit 3 of the Status register is set.
The core identifies that data is present in the input buffer by either polling IBF bit of the Status register or acknowledging an
interrupt when the input buffer interrupt is enabled (IBFCIE in HICTRL register is set to 1).
When the input buffer is full, reading the Status register identifies which address was written to (i.e., check A2 of HIKMST
register). The core can then read the data from the input buffer (HIKMDI). The IBF status bit is cleared when the data input
buffer is read by the core.
Host Data Read from Host Interface Keyboard/Mouse Channel
The output data latch (DBBOUT) is written by the core when it needs to send data to the host. The OBF flag in the Status
register (OBF in HIKMST register) is set to indicate that data is available in DBBOUT. DBBOUT should be written only when
this bit is cleared.
The PC87591x supports polling and interrupt communication schemes with the host. Both Keyboard interrupt (IRQ1) and
Mouse interrupt (IRQ12) are supported.
The core firmware writes to HIKDO register data addressed to the keyboard driver (i.e., generate IRQ1). A write to HIKDO
stores the data to DBBOUT and sets OBF bit. If the IRQ1 interrupt is enabled (OBFKIE in HICTRL register is set to 1), it is
also sent according to the interrupt mode (IRQM field and IRQNPOL bit in HIIRQC register).
The core firmware writes data addressed to the mouse driver (IRQ12) to HIMDO register. A write to HIMDO stores the data
in DBBOUT and sets OBF bit. If the IRQ12 interrupt is enabled (OBFMIE in HICTRL is set to 1); the IRQ12 interrupt is also
sent according to the interrupt mode (IRQM field and IRQNPOL bit in HIIRQC register).
Interrupt Request
16
Interrupts to the Host Processor
through SuperI/O Configuration
or 64
Keyboard
Output Buffer
16
(IRQ1)
Interrupts to the Core
Empty
, the following sequence of events occurs: the data is written to the Data In latch (DBBIN), IBF bit in the Status
Figure 94. Host Interface Keyboard/Mouse Channel (Ports 60,64) Block Diagram
Interrupt Request
(IRQ12)
Mouse
Input Buffer
16
Full
(legacy A2=0), bit 3 of the Status register is cleared. When writing to address 64
16
to obtain the contents of the Status register. The core software can obtain this
STATUS
Host-WR-Data-Buffer
Host-RD-Data-Buffer
(Continued)
279
WR-Mouse
WR-KBD
DBBOUT
Buffer
RD-Input
D0-7
A2
DBBIN
Peripheral Bus
D0-7
SIB Bus
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16
(legacy