pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 363

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host-Controlled Modules and Host Interface
6.2.14 Battery-Backed RAMs and Registers
The RTC has two battery-backed RAMs and 17 registers, used by the logical units themselves. Battery-backup power en-
ables information retention during system power down.
The RAMs are:
The memory maps and register content of the RAMs are shown in Section 6.2.18 on page 371 and illustrated in Figure 122.
The first 14 bytes and three programmable bytes of the Standard RAM are overlaid by time, alarm data and control registers.
The remaining 111 bytes are general-purpose memory.
Registers with reserved bits should be written using the “Read-Modify-Write” method.
All register locations within the device are accessed by the RTC Index and Data registers (at base address and base ad-
dress+1, as defined by RTC configuration registers at index 60
being accessed, and the Data register contains the data to be transferred to or from the location. An additional 128 bytes of
battery-backed RAM (also called Extended RAM) may be accessed via a second pair of Index and Data registers (at base
address and base address+1, as defined by RTC configuration registers in index 62
Access to the two RAMs may be locked. For details, see ”RAM Lock Register (RLR)” in Section 6.1.12 on page 353.
The index of three of the RTC registers is programmable using registers in the RTC logical device bank (part of the SuperI/O
configuration registers). If enabled, these registers override three of the Standard RAM locations; see Section 6.1.12 on
page 353.
6.2.15 RTC Registers
The RTC registers can be accessed at any time during normal operation mode; i.e., when V
operation range. This access is disabled during battery-backed operation. Write operation to these registers is also disabled
if bit 7 of CRD register is 0.
Note: Before attempting to perform any start-up procedures, read the explanation of bit 7 (VRT) of CRD register.
See Section 6.2.18 on page 371 for a detailed description of the memory map for the RTC registers.
This section describes the RTC Timing and Control registers, which control basic RTC functionality.
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.
Standard RAM
Extended RAM
Index
7F
70
73
63
60
16
16
16
16
16
SIO Configuration
Data
}
}
prog. indexes
RAM lock
Base
Index
Figure 122. RTC Module Registers Mapping
7F
0E
0D
00
16
16
16
16
Base+1
Standard Bank
(Legacy 0x70, 0x71)
Data
363
16
(Continued)
and 61
Registers
Standard RAM
(3-byte override by
programmable indexes)
register with
16
). The Index register points to the register location
Base
16
and 63
Index
7F
CC
00
16
16
Base+1
16
Extended Bank
(Legacy 0x72, 0x73)
).
is within the recommended
Data
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