pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 263

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Flash Identification Register (FL_ID)
FL_ID is a shift register that contains device identification information. This information can help to verify the use of the cor-
rect flash programing algorithm and to match downloaded information to the device properties.
Type: Read Only
Bit
Name
Reset
13-11
Bit
10
14
15
4
5
6
7
8
9
R/W1C FMDERR (Flash Data Loss Error). Indicates that a double-buffer overrun error occurred. The bit is cleared
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
31 30 29 28 27 26 25 24 23 2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
by writing 1 to FMDERR bit in Control register. It may be cleared only when FMBUSY bit is cleared (0).
0: No data loss detected (default)
1: A write to a full buffer was detected
FLAEN (Flash Access Enabled).
0: The flash memory protection is set; read, write and erase (except special erase) are disabled
1: The flash memory access through the JTAG serial bus is enabled
BLFF (Blank Flash Flag).
0: The Blank Flash flag is cleared and the core is allowed to execute from it
1: The Blank Flash flag is set and the core is kept in reset, even when flash access is enabled
FMPRGE (Flash Memory Program Enable).
0: Programing the flash memory using JTAG write instructions is disabled (default)
1: Programing the flash memory using JTAG write instructions is enabled
FFMPERE (Flash Memory Page Erase Enable).
0: Flash page erase disabled (default)
1: Flash page erase using the JTAG Erase instruction is enabled
FMSERE (Flash Memory Sector Erase Enable).
0: Flash sector erase disabled (default)
1: Flash sector erase using the JTAG Erase instruction is enabled
FMSPERE (Flash Memory Special Erase Enable).
0: Flash special erase operation disabled (default)
1: Flash special erase operation using the JTAG Erase instructions is enabled
Reserved.
DISVRF (Disable Verify).
0: Enables verification of flash contents after program or erase (default)
1: Disables the automatic verification of flash contents after program or erase;
JTFIE (JTAG To Flash Interface Enabled).
0: Flash access through the JTAG is disabled. Write of 1 to any other bit in this register is ignored, all
1: Interface to the flash through the JTAG is enabled
error flags are cleared, and all other JTAG access flash transactions are ignored (i.e., Capture-DR re-
turns invalid data, Update-DR is ignored) (default).
this speeds up the program or erase speed.
TDI
Reserved
32
15
Figure 88. Flash Identification Register
Reserved
(Continued)
0
FL_ID
7
263
SRID
Description
0
7
SID
SRID
0
0
TDO
ID values
SID
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