pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 222

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
Flash Read, Write and Erase Time
The flash read access time affects the performance of the core. It is therefore recommended to configure the interface to
achieve the maximum performance allowed for the operation frequency. Table 32 lists the access time for each section of
the flash.
Notes:
The Flash Timing Control, included as part of the PC87591x on-chip flash, controls the access time for read, write and erase
operations of the flash memory. This simplifies the handling and use of the flash by the user. To enable operation with var-
ious clock rates the Flash Timing Control includes a set of registers that enable the core to set the parameters. For more
details on the Flash Timing Control, see Section 4.16.3 on page 222.
4.16.3 Flash Interface States and Timing Control
The Flash Timing Control automates six states: Standby, Read, Program, Page Erase, Section Erase and Special Erase.
The widths of pulses used in flash operation are specified in registers and should be set by software based on the operation
frequency of the core clock.
Write cycle timing is not cycle-by-cycle emulated for off-chip Base Memory (SRAM).
For fast read operation, the respective BIU zone should be configured for fast read.
For n wait states, the respective BIU zone should be configured for normal read with n wait states. This provides an
n+2 cycles read throughput.
Sections 0 and 1 are also referred to as the Fast zone.
Standby State
Read State
Program State
Page Erase State
Section Erase State
Main Block
Information Block
The flash does not perform a read, program or erase operation. This is the default state when no operation is per-
formed; current consumption of the flash is therefore minimal.
The flash performs a read operation from either the Main Block or the Information Block. Host or core reads
through the core bus are extended to the required length based on the BIU SZCGF1settings. JTAG interface ac-
cess uses a busy flag to indicate that the read operation is in progress. When the read is completed, the flash re-
turns to Standby state.
The flash programs a byte or word in either the Main Block or Information Block. This state is entered by a core or
host write (with the Program control bit set) or by a JTAG program command. While in this state, the busy indicator
is set. When the program operation is completed, if the verify is enabled, the data is verified and the error bits are
updated accordingly. During Program state, reset is ignored. During programing of the flash, additional writes to
the flash are ignored and reads are delayed until the flash page programing is completed.
The Page Erase state is entered by a core or host write or by a JTAG command when the Page Erase bit is set. An
address within the page specifies which page is to be erased. While in this state, the busy indicator is set. When
the erase operation is completed and the verification is enabled, the data is verified and the error bits are updated
accordingly. During Page Erase state, reset is ignored, additional writes to the flash are ignored and reads are de-
layed until the flash page erase is completed.
The Section Erase state is entered by a core write or by a JTAG command when the Section Erase bit is set. An
address within the section specifies which section is to be erased. While in this state, the busy indicator is set.
When the erase operation is completed, the data is verified and the error bits are updated accordingly. During Sec-
tion Erase state, reset is ignored, additional writes to the flash are ignored and reads are delayed until the flash
section erase is completed.
Block Name
1. See Section 7.5 on page 381 for the values of these parameters.
2. The Zone Configuration register SZCFG1 should be used to set the access speed, based on the cur-
rent operation speed and minimum required access time.
Section Number
Sections 0 and 1
Sections 0 and 1 F
Table 32. Access Time for Flash Sections
(Continued)
FMAX
Max Frequency
F
FMAX
@ 3 clock cycles
@ fast read
222
1,2
as defined in Table 33
Approx. 20 s,
Write Time
as defined in Table 33
as defined in Table 33
Approx. 10 ms,
Approx. 10 ms,
Erase Time
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