pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 327

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pc87591l

Manufacturer Part Number
pc87591l
Description
Lpc Mobile Embedded Controllers
Manufacturer
National Semiconductor Corporation
Datasheet

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Revision 1.07
Host Controller Interface Modules
Wake-Up Event Routing to SMI Enable Register 0 (WK_SMIEN0)
This register is set to 00
events to the SMI signal. Detected wake-up events that are enabled activate the SMI signal regardless of the value of
WK_EN0 register.
Location: Bank 2, Offset 13
Type: R/W
Bit
Name
Reset
5-4
Bit
7-6
0
1
2
3
6
7
3
4
5
RI1 Event to SMI Enable.
0: Disabled (default)
1: Enabled
RI2 Event to SMI Enable.
0: Disabled (default)
1: Enabled
Reserved.
RING Event to SMI Enable.
0: Disabled (default)
1: Enabled
Reserved.
Software Event to SMI Enable.
0: Disabled (default)
1: Enabled
Reserved.
S3 (Request to Change to S3 State). A write of 1 to this bit indicates to the core that the host requests to
change to S3 state. The S state and transition are interpreted, as specified in the ACPI standard for S state
change requests. This bit always reads back 0.
0: Not an S3 state request
1: S3 state setting request
S4 (Request to Change to S4 State). A write of 1 to this bit indicates to the core that the host requests to
change to S4 state. The S state and transition are interpreted, as specified in the ACPI standard for S state
change requests. This bit always reads back 0.
0: Not an S4 state request
1: S4 state setting request
S5 (Request to Change to S5 State). A write of 1 to this bit indicates to the core that the host requests to
change to S5 state. The S state and transition are interpreted, as specified in the ACPI standard for S state
change requests. This bit always reads back 0.
0: Not an S5 state request
1: S5 state setting request
Reserved.
Reserved
7
0
16
16
on V
SMI Enable
Software
Event to
PP
6
0
power-up or Host Domain software reset. It controls the routing of detected wake-up
5
0
(Continued)
Reserved
Description
327
4
0
SMI Enable
Event to
RING
3
0
Reserved
2
0
SMI Enable
Event to
RI2
1
0
SMI Enable
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Event to
RI1
0
0

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