pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 251

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Each ISE interrupt is cleared when ABORT_i and RX_i in DBGISESRC register are both 0. Any bit in DBGISESRC register
is cleared by writing 1 to it (writing 0 is ignored). If there is a new source activity in the same write cycle during which
DBGISESRC register of a specific processor is cleared, the ISE interrupt control asserts ISE again, together with its source
bit.
The ISE interrupt is an active-high pulse. For nested ISE sources, the ISE remains asserted, and the ISE interrupt control
module sets the new source bit to 1.
The DBGMASKS register is not available to the peripheral bus; it is accessed only from the JTAG serial bus when the
SCAN_ABORT_MASK instruction is loaded into the TAP IR.
The ISE signal, together with its source bit, should be asserted in Active or Idle modes for wake-up purposes when the
source is a debugger message or debugger abort. Other functionality should be consistent while changing modes (i.e., dur-
ing wake-up). Full functionality of this module is maintained even when TCK is not toggling.
Clock Synchronization
Some operations are related to TCK, others to the PC87591x main clock and yet others are asynchronous. The PC87591x
logic guarantees correct operation and a meta-stable protected interface in all its operating modes (i.e., Active and Idle).
The core may access the Debugger interface registers only in Active mode.
4.19.4 Flash Interface Functional Description
The Flash interface enables access to the flash through the JTAG serial bus without any core involvement. This enables a
firmware-independent update of flash contents.
The Flash interface is divided into three parts:
Enabling Access to the Flash
The flash can be accessed through the JTAG serial bus in OBD and DEV environments. In IRE and PROG environments,
access cannot be enabled (i.e., write operations to the JTAG Access Enable (JTFIE) bit in the Flash Control and Status reg-
ister, FL_CT_ST, are ignored).
To enable Flash interface access to the flash, use the following sequence:
1. Set Instruction Register (IR) to Flash Control Scan Instruction.
2. Scan in a code with the Flash JTFIE bit in FL_CT_ST register is set to enable access to the PC87591x.
3. Repeat step 2 until the FMBUSY bit in FL_CT_ST register is cleared.
Enabling the flash puts the PC87591x in Reset state. It remains in this state, with the clocks enabled and any core or host
activity disabled, until the Flash interface is again disabled. To disable the flash, clear the JTFIE bit. This releases the
PC87591x from reset and enables the core to start executing the code stored in the flash.
Flash Contents Protection
The flash has a contents protection mechanism that protects the flash contents from read operations and prevents them
from being altered during write transactions. When this mechanism is set, only a special erase that erases the entire flash
can be performed.
When the Blank Flash flag is set, it indicates to the core that the flash has no valid code and that the core should remain in
Reset state until the protection information is changed. Both this flag and the Access Enable flag are part of the flash pro-
tection byte and should be programed after the flash is loaded with data. See Section 4.16.6 on page 226.
Flash Data Read
To read the contents of the flash, perform the following sequence:
1. Enable flash access (if not already enabled).
2. Set the flash to read as follows:
3. Set the address as follows:
Flash Control and Status: Controls flash operations and returns flash status.
Flash Address: Stores the address for flash operations and includes an auto-increment mechanism for speeding up
the flash update process.
Flash Data: Handles flash data for both read and write operations.
a. Set the IR to Flash Control and Status Scan instruction.
b. Scan in a read operation code (8000
a. Set IR to Flash Address Scan instruction.
b. Scan the address of the memory location to be read into the chip.
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