pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 350

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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6.0 Host-Controlled Modules and Host Interface
Memory Range Programing
LPC memory transactions and/or LPC-FWH transactions can be forwarded to the PC87591x shared memory. The Shared
Memory Configuration register defines the transaction type and address range to which the PC87591x responds. The SHBM
strap inputs affect the default settings of the Shared Memory Configuration register to enable boot process from shared
memories. Two memory areas may be individually enabled: a user-defined zone and BIOS memory (either BIOS-LPC
and/or BIOS-FWH spaces).
To enable BIOS support, set the SHBM strap inputs to select any of the BIOS modes (see Section 2.3 on page 53 for de-
tails). The PC87591x responds to LPC memory read and write transactions to/from the BIOS address spaces, shown in
Table 60, as long as BIOS LPC Enable (bit 0) of the Shared Memory Configuration register is set.
The PC87591x responds to LPC-FWH read and write transactions to/from the high memory address range (’386’ mode
BIOS range), shown in Table 60, as long as BIOS FWH Enable (bit 3) of the Shared Memory Configuration register is set.
On host domain hardware reset in BIOS mode, the BIOS LPC Enable bit is set and the BIOS FWH Enable bit is set. The
PC87591x automatically detects the type of host boot protocol in use, via the first completed BIOS read operation after host
domain hardware reset. If the first read is an LPC memory read, the BIOS FWH Enable bit is cleared. If the first read is an
LPC-FWH read, the BIOS LPC Enable bit is cleared. Any other LPC or LPC-FWH transactions are ignored. The bits are
cleared only by the first read operation, allowing software to enable responding to these address ranges by setting the bit.
Figure 112 illustrates this behavior.
The user-defined shared memory enables sharing the memory without using it as a shared BIOS memory. The memory base
address in the host address space and the size of the shared memory are defined in the Shared Memory Base and Shared
Memory Size registers. Address bits above the block size are ignored and are internally replaced with 1s for the purpose of
address translation (e.g., for a 2 Mbyte block size, A21 through A31 are replaced with 1s).
Note: Only hardware-controlled transitions are shown;
other transitions are possible via software writes to the bits.
Host Domain
Hardware Reset
000E 0000
000F 0000
FFE0 0000
FFE0 0000
Memory Address Range
Memory Address Range
16
16
16
16
[SHBM = 0] Shared Disable BIOS
- 000F FFFF
- 000E FFFF
- FFFF FFFF
- FFFF FFFF
Table 61. BIOS-FWH Memory Space Definition
Table 60. BIOS-LPC Memory Space Definition
Figure 112. BIOS Mapping Enable Scheme
First LPC Memory Read
16
16
16
16
BIOS FWH Enable = 0
BIOS LPC Enable = 1
386 mode BIOS range; this is the upper 2 Mbytes of the
memory space. The PC87591x uses the first 21 address
lines and ID field to identify FWH access to the shared
memory.
Extended BIOS range (Legacy); only when Extended
BIOS Enable bit in Shared Memory Range Configuration
register is set.
BIOS Range (Legacy)
386 mode BIOS range; this is the upper 2 Mbytes of the
memory space.
350
BIOS FWH Enable = 1
BIOS LPC Enable = 1
BIOS FWH Enable = 0
BIOS LPC Enable = 0
(Continued)
Description
Description
BIOS FWH Enable = 1
BIOS LPC Enable = 0
First LPC FWH Read
Revision 1.07