pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 7

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Table of Contents
3.0 Power, Reset and Clocks
4.0 Embedded Controller Modules
2.3
2.4
3.1
3.2
3.3
4.1
2.2.12
2.2.13
2.2.14
2.2.15
STRAP PINS ............................................................................................................................. 53
ALTERNATE FUNCTIONS ........................................................................................................ 54
2.4.1
2.4.2
2.4.3
POWER ..................................................................................................................................... 62
3.1.1
3.1.2
3.1.3
RESET SOURCES AND TYPES ............................................................................................... 65
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
CLOCK DOMAINS ..................................................................................................................... 68
BUS INTERFACE UNIT (BIU) ................................................................................................... 69
4.1.1
4.1.2
4.1.3
Mobile System Wake-Up Control (MSWC) .................................................................. 51
Timers and PWM ......................................................................................................... 51
Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ...................... 51
Internal Pull-Up and Pull-Down Resistors ................................................................... 52
GPIO with Alternate Functions .................................................................................... 54
System Configuration Registers .................................................................................. 58
GPIO with Echo Configuration ..................................................................................... 59
Power Planes .............................................................................................................. 62
Power States ............................................................................................................... 62
Power Connection and Layout Guidelines .................................................................. 63
V
V
WATCHDOG Reset and Debugger Interface Reset .................................................... 66
Warm Reset ................................................................................................................. 66
Host Domain Reset ..................................................................................................... 67
Features ...................................................................................................................... 69
Functional Description ................................................................................................. 69
Clock Cycles ................................................................................................................ 71
(Continued)
PP
CC
Power-Up Reset ................................................................................................... 66
Power-Up Reset ................................................................................................... 66
Setting the Environment ...................................................................................... 53
Other Strap Pin Settings ...................................................................................... 53
System Load on Strap Pins ................................................................................. 53
Strap Pin Status Register (STRPST) ................................................................... 54
Register Map ....................................................................................................... 58
Module Configuration Register (MCFG) .............................................................. 58
External Interrupts Configuration Register (EICFG) ............................................ 59
Input to Output Echo Enable Register 1 and 2 (IOEE1 and IOEE2) .................... 60
Using RESET2 Input ............................................................................................ 67
Host Domain Reset Actions ................................................................................. 67
LPC Clock ............................................................................................................ 68
RTC (32 KHz) Clock ............................................................................................ 68
Interface ............................................................................................................... 69
Static Memory and I/O Support ........................................................................... 69
Byte Access ......................................................................................................... 69
Clock and Bus Cycles .......................................................................................... 70
Optional Clock Cycles .......................................................................................... 71
Other Clock Cycles .............................................................................................. 71
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