pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 159

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Frame Select Register (UFRS)
This byte-wide read/write register controls the selection of the frame format, including number of data bits, number of stop
bits and parity. The register is cleared (00
Location: 00 FD28
Type: R/W
Bit
Name
Reset
1-0
5-4
Bit
2
3
6
7
CHAR. Selects the number of data bits per frame. Note that the parity bit is not included in the number of data
bits.
Bits
1 0
0 0:
0 1:
1 0:
1 1:
STP. Programs the number of stop bits to be transmitted.
0: One stop bit transmitted
1: Two stop bits transmitted
XB9. Contains the value of the 9th data bit for transmission only. The bit has no effect while operating with seven
or eight data bits per frame.
0: Transmit 0 as 9th data bit
1: Transmit 1 as 9th data bit
PSEL. Controls the mode of parity bit generation and checking. Note that while operating with nine data bits-
per-frame, the parity bit is omitted. In this case, the value of PSEL has no effect.
Bits
5 4
0 0:
0 1:
1 0:
1 1:
PEN. Enables or disables the generation of a parity bit generation and parity check. Note that there is no parity
bit while operating in the nine data bits-per-frame mode. In this case, this bit has no effect.
0: Parity disabled
1: Parity enabled
Reserved.
Reserved
Description
Frame contains eight data bits
Frame contains seven data bits
Frame contains nine data bits
Loopback mode selected; frame contains nine data bits.
Description
Odd parity
Even parity
Mark (1)
Space (0)
16
7
0
PEN
6
0
16
) on reset.
(Continued)
5
0
PSEL
Description
159
4
0
XB9
3
0
STP
2
0
1
0
CHAR
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