pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 71

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
4.0 Embedded Controller Modules
4.1.3
Basic Bus Cycle
A basic bus cycle comprises one to three clock cycles (depending on the type of bus cycle). Adding extra wait or hold clock
cycles extends the data transfer bus cycles. Every data transfer bus cycle has the T1 and T2 clock cycles, with the exception
of the fast read bus cycle, which has only one clock cycle (T1-2).
T
BIU does not need to generate a bus transaction or as specifically configured pauses between two consecutive transactions.
When more than one T
T
disable times). To do this, either program IPRE and/or IPST in SZCFGn register (or IPST in IOCFG register); see Figure 18
on page 77.
T
cycle; see Figure 23 on page 80.
T1 Cycle Every bus cycle starts with T1. In this clock cycle, the address of the selected device (either external or internal)
is set on the address pins. Write bus cycles never drive data during T1.
T2 Cycle The read T2 bus cycles always sample the data at the end of T2.
The write T2 bus cycles always drive data during T2. If no T
the T2 cycle.
T1-2 Cycle The fast read T1-2 bus cycle is a one-cycle read transaction.
At the start of the clock cycle, the address of the selected device is set on the address pins, and the SELn and RD signals
are activated. At the end of the clock cycle, the BIU samples the data.
T3 Cycle Early write bus cycles always have the T3 clock cycle. No other bus cycles have this clock cycle.
At the start of this clock cycle, SELn (or SELIO) is deactivated; then WR0-1 is deactivated. The address and data remains
valid until T3 is completed. If no T
Optional Clock Cycles
The following clock cycles are optional in a data transfer bus cycle:
TIW Cycle Extend the basic data transfer bus cycle by adding wait clock cycles. To do this, program WAIT in SZCFGn reg-
ister (or IOCFG register) with the required additional wait clock cycles. Wait clock cycles generated by this action are named
TIW (internal wait). TIW cycles are added after T1 and followed by T2 cycles. Data is always driven during wait clock cycles
of a write bus cycle.
T2B Cycle Data of read burst bus cycles is sampled at the end of T2B. If the TBW cycle is not configured, the address is
changed at the start of T2B. Write bus cycles do not have this clock cycle.
TBW Cycle A burst bus cycle can be extended by one wait clock cycle, named TBW. This is done according to WBR in
SZCFGn register. The address is changed at the start of TBW. Write bus cycles do not have this clock cycle.
T
IOCFG register); the address and data (during a write bus cycle) are always valid during these cycles. The data bus is put
in TRI-STATE after the last T
Other Clock Cycles
Special T
This happens due to special activity on the internal core bus. To avoid contention on the memory bus, it is guaranteed that
this clock cycle is followed by a sufficient number of T
The number of T
SZCFGn register.
idle
idle
idle
hold
TIW (Internal Wait)
T2B (T2 burst)
TBW (Burst Wait)
T
clock cycles are also added between an early write and a read bus cycle, and between a late write and a fast read bus
clock cycles can be inserted between two consecutive accesses in different zones (to allow long hold times or buffer
hold
Cycle Clock cycles that are not used for bus cycles are called Idle clock cycles (T
Cycle Hold cycles are added after T2 or T2B (if there is a burst bus cycle) or T3 (according to HOLD in SZCFGn or
Clock Cycles
idle
Cycle During T
idle
cycles that follows is at least the number required by the selected zone as configured in HOLD field in
idle
cycle is requested as a pause, the T
idle
hold
cycles, one of the SEL0-1 signals and the RD signal may be activated for one clock cycle.
.
hold
clock cycles follow, the data bus is put in TRI-STATE after the T3 cycle.
(Continued)
idle
cycles before the next T1 cycle is performed.
hold
71
idle
clock cycles follow, the data bus is put in TRI-STATE after
cycles overlap and only one T
idle
). T
idle
cycles are added when the
idle
cycle is added.
www.national.com