pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 53

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
2.0 Signal/Pin Description and Configuration
2.3
During V
resistors set these signals to 0. These resistors are active only during V
nected to V
Setting the Environment
ENV0 and ENV1 determine the operating environment. Table 6 shows the settings allowed. Pulling both ENV0 and ENV1
to 1 produces unpredictable results. In IRE and OBD environments, the TRIS strap input may be used for floating all the
device signals. In other cases it should be kept low.
Figures 1 on page 24, 3 on page 31 and 4 on page 32 demonstrate how to use the ENV0-1 signals to configure the
PC87591x for IRE, OBD and DEV environments, respectively.
Other Strap Pin Settings
Table 7 provides brief descriptions of other strap inputs. For details on SHBM and TRIS, see Section 5.3 on page 297 and
Section 4.20.4 on page 272, respectively.
System Load on Strap Pins
The loads on the strap pins should not cause the voltage on them to drop below V
rise above V
If the load caused by the system on the strap pins exceeds 10 A, use either an external pull-down resistor to keep the pin
at 0 or a pull-up resistor with lower resistance to keep the pin at 1.
To reduce power consumption, in Idle mode, pins with strap inputs on them and a signal function other than GPIO are put
in TRI-STATE or drive the strap-pin value. For pins with strap inputs that function as GPIO, it is recommended that the ap-
plication drive the strap value as output to the value defined by the strap pin. For pins with strap and address line function-
ality, when the address configuration is enabled, the signal is driven by the hardware to its strap value on reset.
BADDR1-0 SuperI/O Configuration Base Address see Table 47 on page 335
SHBM
TRIS
Strap Pin
STRAP PINS
CC
CC
Power-Up reset, the ENV(0-1), TRIS, SHBM and BADDR strap input signals are sampled. Internal pull-down
IL
may be used to set them to 1.
when they should be low (0). See Section 7.3.2 on page 377.
Disables shared memory with host BIOS
Normal operation
Internal Pull-Down (0)
IRE
OBD
DEV
PROG
1. When set to 1, the PC87591x is put in TRI-STATE
Environment
mode.
Table 6. Environment Pin Settings
Table 7. Other Strap Pin Settings
ENV0
0
0
1
1
53
Enables shared memory with host BIOS
While in IRE and OBD environments, causes PC87591x to
float its output and I/O signals for system test purposes
and clip-on ISE use
(Continued)
ENV1
CC
0
1
0
1
Power-Up reset. An external 10 K resistor con-
External Pull-Up (1)
IH
when the pins should be high (1), or to
TRIS
0
0
0
0
1
1
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