pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 233
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pc87591l
Manufacturer Part Number
pc87591l
Description
Lpc Mobile Embedded Controllers
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L.pdf
(437 pages)
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Revision 1.07
Embedded Controller Modules
Flash Memory Page Erase Time Register (FLPERASE)
The FLPERASE register controls the page erase pulse width. FLPERASE defaults to (09
Location: 00 F8D2
Type: R/W
Flash Memory Section Erase Time Register (FLSERASE)
The FLSERASE register controls the section erase pulse width. FLSERASE defaults to (09
Location: 00 F8D4
Type: R/W
Flash Memory End Time Register (FLEND)
The FLEND register controls the program/page erase end delay time. FLEND defaults to (14
Location: 00 F8D8
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
Bit
Name
Reset
7-0
7-0
7-0
Bit
Bit
Bit
FTPER (Page Erase Pulse Width). This register should be configured based on the currently set core
frequency. See Table 33 on page 223 for details of required values.
FTSER (Section Erase Pulse Width). This register should be configured based on the currently set core
frequency. See Table 33 on page 223 for details of required values.
FTEND (End Delay Count). This register should be configured based on the currently set core frequency. See
Table 33 on page 223 for details of required values.
16
16
16
7
0
7
0
7
0
6
0
6
0
6
0
(Continued)
5
0
5
0
5
0
Description
Description
Description
233
4
0
4
0
4
1
FTPER
FTSER
FTEND
3
1
3
1
3
0
2
0
2
0
2
1
16
) on reset.
16
16
) on reset.
) on reset.
1
0
1
0
1
0
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0
1
0
1
0
0
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