pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 132

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
Note: When CLK1, CLK2, CLK3 and CLK4 are all 0, this is interpreted as a shift mechanism reset. In this case, the PSTAT
register and the shift state machine are reset to their initial state.
PS/2 Input Signal Register (PSISIG)
The PSISIG register is an 8-bit read only register. It provides the current value of the PS/2 port signals.
Location: 00 FE88
Type: RO
Bit
Name
Bit
Bit
3
4
5
6
7
0
1
2
3
4
5
6
7
CLK1 (Enable Channel 1)
0: Forces the PSCLK1 pin low (0) and disables channel 0 of the shift mechanism.
1: Depends on whether or not the shift mechanism is enabled.
CLK2 (Enable Channel 2). Same as bit 3 of this register (described above) but for channel 2.
CLK3 (Enable Channel 3). Same as bit 3 of this register (described above) but for channel 3.
WDAT4 (Write Data Signal Channel 4). Controls the data output to channel 4 data signal (PSDAT4). For more
information, see the description of bit 1 (above).
CLK4 (Enable Channel 4). Same as bit 3 of this register (described above) but for channel 4.
RDAT1 (Read Data Signal Channel 1). The current value of the channel 1 data signal (PSDAT1).
RDAT2 (Read Data Signal Channel 2). The current value of the channel 2 data signal (PSDAT2).
RDAT3 (Read Data Signal Channel 3). The current value of the channel 3 data signal (PSDAT3).
RCLK1 (Read Clock Signal Channel 1). When read, returns the current value of the channel 1 clock signal
(PSCLK1).
RCLK2 (Read Clock Signal Channel 2). When read, returns the current value of the channel 2 clock signal
(PSCLK2).
RCLK3 (Read Clock Signal Channel 3). When read, returns the current value of the channel 3 clock signal
(PSCLK3).
RDAT4 (Read Data Signal Channel 4). The current value of the channel 4 data signal (PSDAT4).
RCLK4 (Read Clock Signal Channel 4). When read, returns the current value of the channel 4 clock signal
(PSCLK4).
When the shift mechanism is enabled (EN bit in PSCON register is set to 1), channel 1 of the PS/2 ports
is enabled.
When the shift mechanism is disabled (EN bit in PSCON register is set to 0), the clock line output buffer
data is 1 (i.e., the signal is pulled high by the pull-up, if enabled, and may be pulled low by an external de-
vice).
RCLK4
16
7
RDAT4
6
RCLK3
(Continued)
5
RCLK2
Description
Description
132
4
RCLK1
3
RDAT3
2
RDAT2
1
RDAT1
Revision 1.07
0