pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 328

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Host Controller Interface Modules
Wake-Up Event Routing to IRQ Enable Register 0 (WK_IRQEN0)
This register is set to 00
events to the assigned MSWC interrupt request (IRQ) channel. Detected wake-up events that are enabled activate the as-
signed IRQ channel regardless of the value of WK_EN0 register.
Location: Bank 2, Offset 15
Type: R/W
5.5.6
For a summary of the abbreviations used for Register Type, see Section 2 on page 34.
Bit
Name
Reset
5-4
Bit
0
1
2
3
6
7
MSWC Core Registers
RI1 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
RI2 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Reserved.
RING Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Reserved.
Software Event to IRQ Enable.
0: Disabled (default)
1: Enabled
Reserved.
Reserved
7
0
MSWCTL1
MSWCTL2
MSWCTL3
HCFGBAL
HCFGBAH
MSIEN2
MSHES0
MSHEIE0
Mnemonic
16
16
on V
IRQ Enable
Software
Event to
PP
6
0
power-up or Host Domain Software reset. It controls the routing of detected wake-up
MSWC Control Status Register 1
MSWC Control Status Register 2
MSWC Control Status Register 3
Host Configuration Base Address Low
Host Configuration Base Address High
MSWC Interrupt Enable Register 2
MSWC Host Event Status Register 0
MSWC Host Event Interrupt Enable Register
Table 46. MSWC Core Register Map
5
0
(Continued)
Reserved
Register Name
Description
328
4
0
IRQ Enable
Event to
RING
3
0
Reserved
Varies per bit
Varies per bit
0
2
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
IRQ Enable
Event to
RI2
1
0
IRQ Enable
Event to
RI1
Revision 1.07
0
0