pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 321

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host Controller Interface Modules
The SMI may be output from the PC87591x using the dedicated SMI signal or by routing SMI to an interrupt request channel
via the device’s configuration registers.
The Wake-Up Event Routing Control register, MSHEIEn, which is controlled by the core, holds an enable bit for each of the
events, which allows selective routing of these events to the core wake-up interrupt (MSWCI) to the MIWU. The core event
is controlled using a separate set of status signals to prevent race conditions when clearing events.
The MSWCI interrupt is a level high interrupt that gathers requests from MSHESn, MSWCTL2 and MSWCTL3 registers.
Once an output event is asserted, it keeps its active state until all set status bits are cleared or masked. This interrupt signal
is connected to the MSWC wake-up input of the MIWU. This enables handling state change requests even in Idle mode.
The MSWC output for this input is connected to the core through the MIWU module, enabling a power state change on in-
terrupt.
Wake-Up Event i
Extension Logic
From Wake-Up
From Host
I/F Module
Wake-Up
Module SMI
Wake-Up
Routing
from IRQs
Detection
Event i
WK_SMIENn.i
WK_IRQENn.i
WK_ENn.i
MSHEIEn.i
Figure 106. SMI and PWUREQ Source Gathering Scheme
PWUREQ Wake-Up Module
IRQi Wake-Up
IRQj Wake-Up
PM2SMI
PM1SMI
Figure 105. Wake-Up Event Routing Scheme
WK_STSn.i
MSHESn.i
(Continued)
321
Event
Routing
Logic
To Peripheral Bus
PWUREQ
SMI
MSWCI
to MIWU
PWUREQ
SMI
IRQ
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