pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 210

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
4.14.4 ACM Operation
Reset
The ACM is initialized by core domain reset (Section 3.2 on page 65 describes the PC87591x reset events).
Upon reset, the ACM is disabled, with all interrupt sources masked and the over/under threshold select set to “below”. All
Event status bits are reset. The trigger division factor, as well as the data sampling delay, are set to their maximum value
(for the slowest ACM operation speed). The comparison threshold is set to zero.
All control, configuration and status registers are reset to their default values, as indicated in Section 4.14.5 on page 212.
Voltage Level Data Buffer registers and the Comparison Result register’s values are invalid until the first measurement oc-
curs (on each of them).
Sampling Delay
This delay separates between the new value being loaded into the D/A converter and the data being sampled into the Volt-
age Level Data Buffer registers and the Comparison Result register. Its value should be longer than the total time required
by the D/A output to settle (within 1/2 LSB of 6 bits) and the comparators to toggle their state.
The value set by SMPDLY field in ACMTIM register is expressed in terms of core CLK clock cycles. The maximum frequency
at which each delay may be used is specified in the register’s description.
Initializing the ACM
The ACM must be initialized before it is enabled and used. The following operations should be done:
After initializations are done, the ACM may be enabled by writing 1 to START bit in ACMCTS register.
Note: Setting any of the above bits/fields during ACM operation may cause unpredictable results.
Select the ACM Mode Control by setting ACMMOD field in ACMCNF register.
Enable interrupts are required using the following bits of ACMCNF register:
— Interrupt from End-of-Measurement Event Enable by setting INTEMEN bit.
— Interrupt from Over/Under Threshold Event Enable by setting INTOUEN bit.
Select Over or Under Threshold mode, using OVUNSEL bit in ACMCNF register.
Set the data sampling delay using SMPDLY field in ACMTIM register.
Select the low power trigger rate by setting T0DIV field in ACMTIM register.
Select the Comparison Threshold Data for wake-up by setting THRSHD field in THRDAT register.
Voltage Ratio to V
Figure 75. Level Data to Input Voltage Ratio Conversion
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Level Data
Revision 1.07