pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 258

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
Instructions
Instructions are entered serially into the Debugger interface logic during an IR scan by using the IR. See Table 39 for the
required binary codes.
Note:
Data registers not selected by the current instruction do not interfere with the operation of the on-chip system logic or with
the selected data registers.
Each instruction enables a single serial data register path to shift data between TDI and TDO in Shift-DR state, as shown in
Table 40.
Instruction codes that are not required to control test logic are equivalent to the BYPASS instruction.
BYPASS
The BYPASS instruction operates the BYPASS register. This register contains a single shift register stage and provides a min-
imum-length serial path between the TDI and TDO pins of a component when no test operation is needed for that component.
This allows more rapid movement of test data to and from other board components that are required to perform test operations.
The BYPASS instruction selects BYPASS register to be connected for serial access between TDI and TDO in the Shift_DR state.
If the BYPASS instruction is selected, all other data registers continue their normal functionality.
Flash Support Instructions
Flash Control Scan
The Flash Control Scan instruction switches the data scan path to FL_CT_ST register. During this instruction, the length of
the scan chain is 16 bits. In this case, the Control and Status register of the flash can be scanned. In the Capture-DR state
of the TAP controller, the Status register is latched into the FL_CT_ST register chain. During the Update-DR state, the Con-
trol register is loaded with the contents of FL_CT_ST register. Some bits are shared between the two registers and operate
as read/write or read/write 1 to clear.
Device I/D Scan
The Device I/D Scan instruction switches the data scan path to FL_ID register. During this instruction, the length of the scan
chain is 32 bits. In this case, SID and REVID registers of the SuperI/O are read and their contents are sampled in the
Capture-DR state. No updates are made during the Update-DR state.
Flash Address Scan
The Flash Address Scan instruction switches the data scan path to FL_ADDR register. During this instruction, the length of
the scan chain is 32 bits. In this case, the Address register of the flash can be scanned. In the Capture-DR state of the TAP
controller, the flash address is latched into the FL_ADDR chain. During the Update-DR state, if the Block ID field is other
than ‘0000’, Flash Address register is loaded with a new value from FL_ADDA and the Valid bit in the data register is cleared.
After Flash Address register is loaded, a read operation from the array is performed, the result is stored in the Flash Read
Data buffer, and the Data Read buffer Valid bit is set.
D11 D10 D9 D8 D7
L4
x
x
x
0
0
0
0
0
0
x
x
x
1. D0 is the nearest to the serial output.
2. “X” means ignore.
3. Debugger abort is generated by SCAN_RX when PID=‘1111’.
L3
x
x
x
0
0
0
0
0
0
x
x
x
L2
0
0
0
0
0
0
x
x
x
x
x
x
L1
x
x
x
0
0
0
0
0
0
x
x
x
L0
x
x
x
0
0
0
0
0
0
x
x
x
other
PID3 PID2 PID1 PID0
D6
0
0
0
0
1
1
x
x
x
x
x
x
D5
x
x
x
0
0
0
1
0
1
x
x
x
Table 39. IR Instruction Binary Codes
D4
x
x
x
0
0
1
1
1
1
x
x
x
(Continued)
D3
x
x
x
0
1
0
0
0
0
x
x
x
D2 D1 D0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
258
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1 BYPASS
0 BYPASS (Reserved for Scan)
0 BYPASS
1 Flash Control Scan
1 Device I/D Scan
1 Flash Address Scan
1 Flash Data Read Scan
1 Flash Data Write Scan
1 Flash Erase Scan
1 BYPASS
0 SCAN_RX
1 SCAN_TX
1 SCAN_ABORT_MASK
0 ASSERT_DBG_RST
Instruction
Revision 1.07