pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 193

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
All DAC channels are automatically disabled when entering Idle mode if ENIDLE bit in DACCTRL register is cleared to 0.
This happens regardless of the state of DACENn (n=0 to 3) bit in DACCTRL register. In this case, the DA0-3 outputs drive
0V.
If the ENIDLE bit is set to 1, entering the Idle mode does not affect DAC operation, and DA0-3 outputs drive the voltage level
set by DACDATn (n=0 to 3) registers.
4.12.5 DAC Registers
The DAC interfaces with the core using one control and four data registers. These registers are mapped to the core address
space, as defined in Appendix A on page 408.
DAC Register Map
DAC Control Register (DACCTRL)
This register controls the operation of the DAC module. DACCTRL is cleared (00
Location: 00 FF40
Type: R/W
Bit
Name
Reset
7-5
Bit
0
1
2
3
4
DACEN0 (DAC Channel 0 Enable). Enables the DAC channel. The DA0 output pin drives a voltage level,
according to the value written into the corresponding DACDAT0 register.
When cleared, the DA0 output pin drives 0V.
0: Disabled (default)
1: Enabled
DACEN1 (DAC Channel 1 Enable). Same as DACEN0 bit description, using DA1 output and DACDAT1
register.
DACEN2 (DAC Channel 2 Enable). Same as DACEN0 bit description, using DA2 output and DACDAT2
register.
DACEN3 (DAC Channel 3 Enable). Same as DACEN0 bit description, using DA3 output and DACDAT3
register.
ENIDLE (Enable in Idle). Controls the DAn (n=0 to 3) outputs in Idle mode.
0: Disabled - DAn outputs drive 0V (default)
1: Enabled - DAn outputs according to DACENn bits and DACDATn registers
Reserved.
16
7
0
Mnemonic
DACCTRL
DACDAT0
DACDAT1
DACDAT2
DACDAT3
Reserved
6
0
DAC Control
DAC Data Channel 0
DAC Data Channel 1
DAC Data Channel 2
DAC Data Channel 3
(Continued)
5
0
Register Name
ENIDLE
Description
193
4
0
DACEN3
3
0
16
) on reset.
DACEN2
2
0
Type
R/W
R/W
R/W
R/W
R/W
DACEN1
1
0
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DACEN0
0
0