pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 138

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
In this case, the current value of the counter is transferred to the corresponding capture register; following this, the counter
is preset to FFFF
while reducing CPU overhead.
The pulse width of the input signal on TAn and TBn must be equal to or greater than one system clock cycle (see
Section 7.6.10 on page 399 for additional details). The values captured in TnCRA register at different times reflect the
elapsed time between transitions on the TAn pin. The same is true for TnCRB register and the TBn pin. Each input pin can
be configured to sense either rising or falling edge transitions.
The timer can be configured to generate interrupts on reception of a transition on either TAn or TBn. The interrupts can be
enabled or disabled separately for TAn or TBn by TAnIEN and TnBIEN bits. An underflow of TnCNT1 can also generate an
interrupt if the interrupt was enabled by TnCIEN bit. All three interrupts have individual pending flags. See Section 4.7.4 on
page 140 for detailed information.
Timer/counter 2 can be used as a “simple” system timer in this mode of operation. The TnCNT2 counter counts down with
the clock selected via the counter 2 clock selector, and TnCNT2 can be configured to generate an interrupt on underflow if
the interrupt was enabled by TnDIEN bit. See Section 4.7.4 on page 140 for detailed information.
Note that TnCNT1 cannot operate in the “Pulse Accumulate” or “External Event Counter” modes of operation since TBn input
is used as a capture input. Selecting either “Pulse Accumulate” mode or “External Event Counter” mode for TnCNT1 causes
TnCNT1 to stop. However, all available clock source modes may be selected for TnCNT2. Thus it is possible to use TnCNT2
to determine the number of capture events on TBn or the elapsed time between capture events on TBn.
Mode 3, Dual Independent Timer
Dual Independent Timer mode can be used for a wide variety of system tasks such as the generation of periodic system
interrupts, based either on the prescaled clock or external events on TBn. The timer can also toggle TAn pin on underflow,
allowing the simple generation of a processor-independent 50% duty cycle PWM signal on TAn. In this mode, TnCNT1
counts down and reloads from TnCRA on underflow while TnCNT2 is reloaded from TnCRB on underflow.
In this mode, the timer is configured to operate as a dual independent system timer or dual external event counter. In addi-
tion, timer/counter 1 can generate a 50% duty cycle PWM signal on the TAn pin. The TBn pin can be used as an external
event input or pulse accumulate input and forms the clock source to either counter 1 or counter 2, as described above. Both
counters can also be operated using the prescaled system clock. Figure 49 shows a block diagram of the timer in mode 3.
Timer1
Timer 2
Clock
Clock
16
. Using this approach enables an external signal’s on-time, off-time or period to be directly determined,
Timer/Counter 1
Timer/Counter 2
TnCNT1
Capture A
Capture B
TnCRA
TnCRB
TnCNT2
Figure 48. Mode 2, Dual Input Capture
(Continued)
Preset
Preset
Underflow
138
Underflow
TAEN
TBEN
TCIEN
TAIEN
TBIEN
TDIEN
TCPND
TBPND
TAPND
TDPND
Interrupt 1
Interrupt 1
Interrupt 1
Interrupt 2
Timer
Timer
Timer
Timer
TBn
TAn
Revision 1.07