pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 352

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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6.0 Host-Controlled Modules and Host Interface
Shared Memory Base Address Low Byte Register
This register describes the low byte for the user-defined memory zone mapped to the shared memory (decoded as bits 23
to 16 of the 32-bit address range, bits 15-0 are 0). This register is reset to 00
Location: Index F6
Type: R/W
Shared Memory Size Configuration Register
This register defines the size of the user-defined memory zone mapped to the shared memory. This register is reset to 00
on host domain hardware reset.
Location: Index F7
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
3-0
7-4
Bit
7-0
Bit
User-Defined Memory Zone Address Low. Defines the lower eight bits of the user-defined memory block base
address. The base address should be aligned on the selected block size.
User-Defined Memory Zone Size. Defines the size, in bytes, of the zone window. The size is defined as an
exponent of two, using the equation: NumOfBytes = 2
zone must always be aligned to the window size (i.e., for a 128 Kbyte window, the 17 LSBs of the address
should be zero).
Bits
3 2 1 0 Size (Bytes)
0 0 0 0 64K (default)
. . .
0 1 0 1 2M
Other
Reserved.
16
16
Reserved
7
0
7
0
6
0
6
0
Reserved
User-Defined Memory Zone Address Low
5
0
5
0
Description
Description
352
4
0
4
0
n
(where, n = User-Defined Memory Zone size+16). The
(Continued)
3
0
3
0
16
User-Defined Memory Zone Size
on Host Domain Hardware reset.
2
0
0
2
1
0
1
0
Revision 1.07
0
0
0
0
16