pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 332

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Host Controller Interface Modules
MSWC Host Event Status Register 0 (MSHES0)
This register holds information similar to that in WK_STS0 register. The same event that causes a WK_STS0 bit to be set
sets the respective bit in MSHES0 register. Clearing bits is done for each of the status registers separately. This register is
reset to 00
of this register behaves in a special way on set and clear, as described below.
Location: Offset 00 FCCE
Type: R/W1C
Bit
Name
Reset
Bit
Name
Reset
Bit
5-1
Bit
0
1
2
0
6
7
RI1 Event Status.
0: Event not detected (default)
1: Event detected
RI2 Event Status.
0: Event not detected (default)
1: Event detected
Reserved.
EIRTCAL (Enable Interrupt on RTC Alarm). Mask generation of interrupt to the core on setting of the RTC
Alarm bit in MSWCTL1 register.
0: Interrupt disabled (default)
1: Generate a level high interrupt when the RTC Alarm bit is set
EIACPIS5-1 (Enable Interrupt ACPI request for S5 through S1). Mask generation of interrupt to the core on
changes to ACPISi (i=5-1) bit in MSWCTL2 register. An interrupt enable for ACPIS0 is enabled when any of
these bits is set.
0: Interrupt disabled (default)
1: Generate a level high interrupt on any change to the ACPISi bit
EICFGPBM (Enable Interrupt SuperI/O Configuration Register D Power Button Mode). Mask generation of
interrupt to the core on changes to CFGPBM bit in MSWCTL2 register.
0: Interrupt disabled (default)
1: Generate a level high interrupt on any change to the CFGPBM bit
EICFGPSO (Enable Interrupt SuperI/O Configuration Register D Power Supply Off). Mask generation of
interrupt to the core on changes to CFGPSO bit in MSWCTL2 register.
0: Interrupt disabled (default)
1: Generate a level high interrupt on any change to the CFGPBM bit
16
on V
Module IRQ
EICFGPSO EICFGPBM
Status
Event
CC
7
0
7
0
power-up or Host Domain Software reset. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6
16
Software
Status
Event
6
0
6
0
EIACPIS5
5
0
5
0
(Continued)
Reserved
EIACPIS4
Description
332
Description
4
0
4
0
EIACPIS3
Status
Event
RING
3
0
3
0
EIACPIS2
Reserved
0
2
0
2
EIACPIS1
Status
Event
RI2
1
0
1
0
EIRTCAL
Status
Event
RI1
Revision 1.07
0
0
0
0