pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 44

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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2.0 Signal/Pin Description and Configuration
2.2.5
Development System Support
BE1-0
BRKL_RSTO N/A
BST2-0
CBRD
PFS
PLI
TCK
TDI
TDO
TINT
TMS
Signal
128-Pin
N/A
N/A
N/A
N/A
N/A
78
80
79
77
81
LQFP
121,129 O
76
69,
63-62
120
70
75
106
108
107
105
109
176-Pin
LQFP
I/O
O
O
O
O
O
O
I
I
I
I
IN
Buffer
Type
IN
O
O
O
O
O
O
OD
T
IN
IN
/O
1/2
1/2
1/2
1/2
1/2
1/2
TS
T
T
2
1/2
Power
Well
V
V
V
V
V
V
V
V
V
V
V
44
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
(Continued)
Byte Enable bits 1 and 0 on monitor bus
cycles.
Break Line and Reset Out. When the Core
bus is active, the pin is used as a BRKL input.
It Indicates to the core that a breakpoint is
needed once the currently fetched instruction
goes into execution.
When the core bus is not active, the signal is
used as a RSTO output. It indicates to the
system that an internal reset to the core and
its peripherals occurred.
Bus Status bits 2-0 on monitor bus cycles. In
DEV environment, these pins allow monitoring
of the external bus cycles. When OBR bit in
BCFG register is set, the internal bus cycles
are also visible on the external bus. See also
Table 41 on page 273.
Core Bus Read Status on monitor bus
cycles.
Available in all modes. See Section 4.1.9 on
page 81.
Pipe Flow Status.
Pipe Long Instruction.
JTAG Test Clock.
JTAG Test Data In.
JTAG Test Data Out.
JTAG Test Interrupt.
JTAG Test Mode Select.
Description
Revision 1.07