pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 90

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
4.2.5
Intermittent Operation Mode
When BPC bit in DMACNTLn is 0, channel n is in Intermittent mode. In this mode, the DMAC channel relinquishes the bus
after each transaction, regardless of the state of its DMA request input. In this way, the DMAC gives the core (and other
DMA channels) a chance to use the bus, even if a DMA device needs the bus for multiple transfers.
Continuous Operation Mode
When BPC bit in DMACNTLn register is 1, channel n is in Continuous mode. In this mode, a DMAC channel uses the bus
continuously, as long as its request is active and BLTCn > 0. This allows the channel to utilize the full bandwidth of the bus.
The activity of this channel cannot be interrupted by any other internal bus master, including higher priority DMAC channels.
It is the system designer’s responsibility to limit the duration of the DMA request to prevent bus starvation.
Bus Policy
Bus State
CLK
DMRQi
ADDR
DMACKi
Figure 30. DMAC Direct Bus Cycles in Intermittent Mode, DMRQ Asserted Constantly.
Bus State
CLK
DMRQi
ADDR
DMACKi
Figure 31. DMAC Direct Bus Cycles in Continuous Mode - External Bus
T1
ADCA
T1
T2
ADCA
(Continued)
T2
Tidle
T1
90
Core Cycle Address
T1
ADCA
T2
T2
Tidle
Tidle
T1
Core Cycle Address
ADCA
T2
Revision 1.07