pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 221

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Flash Page Organization and Erase Options
A flash erase operation changes all bits in the erased memory area to 1s. The minimum flash portion that can be erased is
a page. A byte address can be written once before the next erase.
The erase process includes verification. During an erase, a busy indicator is turned on. On completion, the busy indicator is
turned off, an error indicator is turned on if an error is detected and the on-chip flash returns to standby.
A flash program operation changes bits that are 1 to 0. A flash program operation may performed on bytes or words.
The PC87591x flash is organized in rows, grouped in pages and partitioned into sections as follows:
The PC87591x provides three erase operations:
Notes:
Page Erase - erase either one page of the flash Main Block or Information Block.
Section Erase - erase an entire section.
Special Erase - erase the entire flash (except factory parameters).
The high voltage required for flash operation is generated on-chip from V
Flash endurance: 10,000 write-erase cycles (minimum).
The PC87591L flash is guaranteed for five write-erase cycles only.
Data retention: more than 100 years at room temperature.
Information Block Factory Parameters
(Base Memory)
Memory Area
Main Block
Information Block
Main Block
1. Additional read and/or write protection may apply according to the setting of the software
2. Read and write operations are enabled only if the Flash Access Enable bit (FLAEN in
3. In DEV Environment, the Base Memory is implemented using an off-chip SRAM, thus any
1. In the PC87591L, the main block is in addresses 00 0000
2. Available only in the PC87591S.
controlled protection mechanism.
FL_CT_ST register) is 1 (see page 262). When the Flash Access Enable bit is cleared,
only a special erase may be performed.
access by the core and/or host is routed to it. Host access limitations apply in DEV envi-
ronment. The core is allowed full read and write access to the off-chip Base Memory.
Block
Table 30. PC87591x Flash Read/Write/Erase Permission Matrix
Core Boot Block
Host Boot Block
Other
Protection Word
Section Name
Table 31. PC87591x Section and Page Organization
Environment
Section 0
Section 1
Section 0
Section 1
Interface
(Continued)
1
2
00 0000
01 0000
Address Range
080
000
IRE, OBD & DEV
RWE
Host
RO
NA
NA
NA
16
16
16
16
221
3
3
- 0FF
- 00 FFFF
- 01 FFFF
1
3
- 07F
16
16
RWE
RWE
Core
RO
RO
RO
16
16
3
3
3
16
CC
- 000FFF
OBD & DEV
.
JTAG
RWE
RWE
RWE
RWe
RO
Page Size
512 bytes
512 bytes
128 bytes
128 bytes
16
2
.
Parallel I/F
PROG
RWE
RWE
RWE
RWE
RWe
2
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