pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 280

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
The host processor identifies that data is present in the output buffer by either polling the Status register (reading address
64
60
register is set to 000
register is set to 0).
The core can read OBF bit to identify when the output buffer is empty and ready for a new data transfer. When the Output
Buffer Empty interrupt to the core is enabled (OBECIE in HICTRL register is set to 1), the interrupt signal to the ICU is set
high if the output buffer is empty (OBF=0).
5.1.3
The module has four registers, described below. The base address for each may be configured individually. For legacy op-
eration, they should be configured to 60
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.
Host Interface Register Map
Data Out Buffer Register (DBBOUT, Legacy 60
This register allows the host to read DBBOUT register while clearing OBF bit in the Status register. If the host interrupts are
level (IRQM in HIIRQC register is 000
(OBECIE in HICTRL register is set to 1), reading this register asserts it (high).
Location: As defined in LDN 06
Type: R
Bit
Name
16
16
7-0
Bit
) or responding to IRQ1 or IRQ12. When this data is available, the host can read it using a read operation from address
. Reading from address 60
Host Interface Registers
Keyboard/Mouse DBBOUT Data.
Offset
60
64
60
64
7
2
16
16
16
16
) and the hardware interrupt is enabled, IRQ1 or IRQ12 are de-asserted (low if IRQNPOL in HIIRQC
DBBOUT
STATUS
DBBIN
COMAND
Mnemonic
16
16
clears the OBF flag. In addition, when the host interrupt is in level mode (IRQM in HIIRQC
6
registers, index 60
2
), the interrupt is de-asserted. If the core interrupt on output buffer empty is enabled
16
and 64
Data Out Buffer
Status
Data In Buffer
Command In Buffer
5
16
Keyboard/Mouse DBBOUT Data
(see Section 6.1.10 on page 348).
16
(Continued)
16
and 61
)
Register Name
Description
280
4
16
3
2
Type
W
W
R
R
1
Revision 1.07
0