pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 59

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
2.0 Signal/Pin Description and Configuration
External Interrupts Configuration Register (EICFG)
The EICFG register is a read/write, byte-wide register. It enables the use of some of the external interrupts. The EICFG bits
have impact only when the pin is configured to its GPIO function. EICFG is cleared (00
Note that some of the pins that have an external interrupt (not controlled by the EICFG register) have an alternate function
that is an input. When a pin’s alternate function is selected, its interrupt function is also enabled.
The format of EICFG is as follows:
Location: 00 FF00
Type: R/W
2.4.3
Some of GPIO pins may be paired to generate an input to output echoing with software masking. The input GPIO are input
ports (Px or Py) with a wake-up function. The output ports are a Px type enhanced with the echo mechanism, as described
in Section 4.5.2 on page 114. The input echoing is enabled only when the respective Echo Enable bit in IOEE1-2 registers
is set. The input port should be configured to enable the interrupt function.
Bit
Name
Reset
4-3
6-4
7-2
Bit
Bit
2
7
0
1
GPIO with Echo Configuration
EXMEM16 (16-bit-Wide Expansion Memory). Enables the use of the 16-bit-wide Expansion memory, when the
ENEMEM is set. The bus width indicated in this register should be the same as the bus width defined in Zone
0 of the BIU (SEL0).
0: The External Memory to be eight bits wide
1: Enables the use of a 16-bit-wide External Memory
CLKOM (Clock Out Mode). Selects the mode of operation of the CLKOUT signal. This field is in effect only
when this signal is set for output.
Bits
4 3
0 0:
0 1:
1 0:
1 1:
Reserved.
GTMON (Go-to Target Monitor Set Flag). This bit is set to indicate that the code should jump to the beginning
of the Target Monitor (TMON). The reset routine of the application should check this bit and behave accordingly.
Once cleared, this bit can not be set by software.
EXWINT45 (Enable EXWINT45).
0: EXWINT45 input is blocked (disabled) while not being read as a GPIO.
1: EXWINT45 input is open; this enables the detection of changes on the input to trigger interrupts.
EXWINT46 (Enable EXWINT46).
0: EXWINT46 input is blocked (disabled) while not being read as a GPIO.
1: EXWINT46 input is open; this enables the detection of changes on the input to trigger interrupts.
Reserved.
Description
Reserved (default)
CLK - a clock at the core frequency is driven out
32.768 KHz clock output
Reserved
16
7
0
6
0
5
0
Reserved
Description
Description
59
4
0
(Continued)
3
0
16
2
0
) on reset.
EXWINT46 EXWINT45
1
0
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