pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 247

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
HFCG Control Register 2 (HFCGCTRL2)
The HFCGCTRL2 register sets the frequency multiplier’s operating parameters. On V
Debugger Interface reset, it is initialized to 00
Location: 00 FFAE
Type: Varies per bit
Bit
Name
Reset
7-5
Bit
0
1
2
3
4
R/W1C SCESTR (SIO Clock Enable Start). Indicates that a rising edge was detected on the SENABEL
R/W1C SCESTP (SIO Clock Enable Stop). Indicates that a falling edge was detected on the SENABEL
R/W1C MONERR (Monitor Error). Indicates that a 48 MHz monitor error was detected during the last
Type
RO
RO
SIO ENABLE (Enable Host Domain Clock). Provides the status of the SuperI/O enable/disable
command. Any data written to this bit is ignored.
0: Disabled
1: Enabled
signal. When set, an interrupt is sent to the ICU (level high). Cleared by writing 1 to it. This interrupt
may be masked only in the ICU.
0: No rising edge on SENABLE was detected (default)
1: A rising edge on SENABLE was detected and an interrupt is sent to the ICU
signal. When set, an interrupt is sent to the ICU (level high). Cleared by writing 1 to it. This interrupt
may be masked only in the ICU.
0: No falling edge on SENABLE was detected (default)
1: A falling edge on SENABLE was detected and an interrupt is sent to the ICU
WATCHDOG or Debugger Reset process. Note that this bit is cleared by all resets except WATCHDOG
and Debugger Interface resets. Once set, this bit is cleared by writing 1 to it.
0: No error detected (default)
1: 48 MHz monitor detected an out of range frequency
96MON (96 MHz Oscillations On). Indicates the oscillation frequency at which the HFCG is operating.
0: HFCG is oscillating as defined by the HFCGM and HFCGN. The core clock is identical to HFCG fre-
1: HFCG is oscillating at 96 MHz. The core clock is pre-scaled as defined by HFCGP.
Reserved.
16
7
0
quency.
Reserved
6
0
(Continued)
16
5
0
.
96MON
247
4
0
Description
MONERR
3
0
SCESTP
CC
0
2
power-up, WATCHDOG reset and
SCESTR
1
0
SENABLE
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