pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 96

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
DMA Status Register (DMASTATn)
A byte-wide, read with write 1 to clear register that holds the status information for the DMAC channel. On reset, the imple-
mented bits are initialized to 0. The reserved bits always return zero when read.
The format of the DMASTATn register is shown below.
Location: Channel 0 - 00 FA1E
Type: R/W1C
Bit
Name
Reset
7-4
Bit
0
1
2
3
1. The VLD, OVR and TC bits are sticky (once set by the occurrence of the specific condition, they remain set until
explicitly cleared by software). These bits can be cleared individually by writing a value into the DMASTATn reg-
ister with the bit positions to be cleared set to 1; writing 0 to these bits has no effect.
TC
(BLTCn register reached 0).
OVR
CHAC (Channel Active). Continuously reflects the active or inactive status of the channel and is therefore read
only. Data written to CHAC bit is ignored.
0: Indicates that the channel is inactive
1: Indicates that the channel is active (CHEN bit in DMACNTLn register is 1 and BLTC > 0)
VLD
transferred are valid.
Writing to the BLTRn register sets this bit to 1.
It is cleared to 0 in the following cases:
Reserved.
Channel 1 - 00 FA3E
Channel 2 - 00 FA5E
Channel 3 - 00 FA7E
1
In double buffered operation (OT bit in DMACNTLn register is 0):
OVR is set to 1 when the present transfer is completed (BLTC = 0), but the parameters for the next transfer
(address and block length) are not valid.
In auto initialize operation: (OT bit in DMACNTLn register is 1)
OVR is set to 1 when the present transfer is completed (BLTC = 0), but TC bit is still set to 1 (e.g., the software
did not serve the last interrupt).
In single buffer operation:
This bit is ignored.
The present transfer is completed, and the ADRAn, ADRBn (Indirect mode only) and BLTR registers are copied
to the ADCAn, ADCBn (Indirect mode only) and BLTCn registers, respectively.
Writing 1 to VLD bit; (writing zero has no effect).
1
1
(Terminal Count). When set to 1, indicates that the transfer was completed by a terminal count condition
(Transfer Parameters Valid). Specifies whether the transfer parameters for the next block to be
(Channel Overrun).
7
0
16
16
16
16
6
0
Reserved
(Continued)
5
0
Description
96
4
0
VLD
3
0
CHAC
0
2
OVR
1
0
TC
Revision 1.07
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