pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 406

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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7.0 Device Specifications
7.6.15 LCLK and RESET1-2
Symbol
1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at fre-
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across
3. The minimum RESET1-2 slew rate applies only to the rising (de-assertion) edge of the reset signal, and ensures
t
t
t
CYC
HIGH
LOW
quencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be
changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic)
and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state.
the minimum peak-to-peak portion of the clock wavering as shown below.
that system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range.
-
-
1
0.3 V
0.4 V
DD
0.5 V
LCLK Cycle Time
LCLK High Time
LCLK Low Time
LCLK Slew Rate
RESET1-2 Slew Rate
DD
DD
2
(Continued)
0.6 V
t
HIGH
3
DD
Parameter
Figure 166. LCLK Waveform
t
CYC
406
0.2 V
t
LOW
DD
Min
30
11
11
50
1
0.4 V
(minimum)
Max
4
DD
P-to-P
mV/ns
Units
V/ns
Revision 1.07
ns
ns
ns