pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 91

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
4.2.6
The DMAC operates in three different block transfer modes - single transfer, double buffer and auto-initialize. Select the ap-
propriate mode according to the character of the block transfer.
Single Transfer Operation
This mode provides the simplest way to accomplish a single block data transfer.
Initialization
1. Write the two block transfer addresses and byte count into the corresponding ADCAn, ADCBn and BLTCn counters, re-
2. Program the OT bit for Non-Auto-Initialize mode, and clear EOVR bit in DMACNTLn register to 0. Clear to 0 VLD bit in
3. Set CHEN bit in DMACNTLn register to 1; the channel activates and responds to DMAC transfer requests.
Termination
When the BLTCn counter reaches 0:
Double Buffer Operation
This mode allows the software to set up the next block transfer specification while the current block transfer proceeds. This
mode is used for preparing the next buffer for use in a multi-buffer operation (e.g., the alternate buffer in a double-buffer
scheme).
Initialization
1. Write the two block transfer addresses and byte count into the ADCAn, ADCBn and BLTCn counters, respectively. The
2. Program OT bit in DMACNTLn register for Non-Auto-Initialize mode.
3. Set CHEN bit in DMACNTLn register to 1; the channel activates and responds to DMAC transfer requests.
4. While the current block transfer proceeds, write the addresses and byte count for the next block into the ADRAn, ADRBn
Continuation / Termination
When the BLTCn counter reaches 0:
If VLD bit is 1:
If VLD bit is 0:
Note:
ADCB and ADRBn are used only in indirect (memory-to-memory) transfer. In Direct (Fly-By) mode, the DMAC does not use
them and therefore does not copy ADRBn into ADCBn.
spectively. The BLTCn counter should be written last.
DMASTATn register.
The transfer operation terminates.
TC bit in DMASTATn register is set to 1, and CHAC is cleared to 0.
A level interrupt is generated (if enabled by ETC bit in DMACNTLn register).
BLTCn counter should be written last.
and BLTRn registers. The BLTRn register should be written last.
TC bit in DMASTATn register is set to 1.
A level interrupt is generated (if enabled by ETC bit in DMACNTLn register).
The DMAC channel checks the value of VLD bit.
The channel copies the ADRAn, ADRBn and BLTRn values into ADCAn, ADCBn and BLTCn. The BLTCn counter
should be written last.
Clears VLD bit to 0.
Becomes ready to start the next block transfer (on the next DMA request).
The transfer operation terminates.
The channel sets OVR bit in DMASTATn register to 1.
Clears CHAC bit to 0.
A level interrupt is generated (if enabled by EOVR bit in DMACNTLn register).
Operation Modes
(Continued)
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