pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 231

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Flash Memory Status Register (FLSR)
This register provides the on-chip flash status. It is cleared (00
Location: 00 F8C2
Type: Varies per bit
Flash Memory Pre-Scaler Register (FLPSLR)
The FLPSLR register selects the pre-scaler divider ratio. FLPSLR defaults to (00
Location: 00 F8C4
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
7-5
Bit
3-0
7-4
Bit
0
1
2
3
4
R/W1C EERR (Erase Error). Indicates an error in erasing the flash by the core. It is cleared by writing 1 to it.
R/W1C PERR (Program Error). Indicates an error in writing to the flash by the core. It is cleared by writing 1
R/W1C DERR (Data Loss Error). Indicates that a double-buffer overrun error has occurred during core access.
FTDIV (Pre-Scaler Divider Value). This register should be configured based on the currently set core
frequency. See Table 33 on page 223 for details of required values.
Reserved.
Type
RO
RO
Writing 0 is ignored. This bit may be cleared only when the FMBUSY bit is cleared (0).
0: No program error detected (default)
1: An error occurred during erase
to it. Writing 0 is ignored. This bit may be cleared only when the FMBUSY bit is cleared (0).
0: No program error detected (default)
1: An error occurred during program
FMBUSY.
0: The embedded flash is ready to accept operations
1: The embedded flash is not accessible since the PC87591x clocks are not ready or the embedded flash
FMLFULL (Double-Buffer Full). Indicates that the core can not write to the flash since its buffer is full.
0: There is at least one word empty in the flash double buffer. If IENPROG is set (1), in the Flash Memory
1: The double-buffer is full
It is cleared by writing 1 to the DERR bit. Writing 0 is ignored. This bit may be cleared only when the
FMBUSY bit is cleared (0).
0: No data loss detected (default)
1: A write to a full buffer was detected
Reserved.
16
16
7
0
7
0
is busy programing or erasing
Control register, an interrupt request to the ICU is active.
Reserved
6
0
6
0
Reserved
(Continued)
5
0
5
0
DERR
Description
231
4
0
4
0
16
Description
) on reset.
FMLFULL
3
0
3
0
16
) on reset.
FMBUSY
2
0
2
0
FTDIV
PERR
1
0
1
0
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EERR
0
0
0
0