pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 259

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Embedded Controller Modules
(Continued)
Flash Data Read Scan
The Flash Data Read Scan instruction switches the data scan path to FL_DATA register. During this instruction, the length
of the scan chain is 18 bits. In the Capture-DR state, the Flash Read Data buffer and the two status bits are loaded into the
shift register and the Valid bit is cleared. The Error bit indicates any error that occurred during the read operation.
If the Valid bit read was cleared, the data and error fields should be ignored. If the Valid bit read was set, the address is
incremented after the Capture-DR state. A data read from the memory is performed, placing the data in the Flash Read Data
buffer and setting the Valid bit.
When the flash address is in the flash main block or Information block, the data read is one word and the address increment
is two.
Flash Data Write Scan
The Flash Data Write Scan instruction switches the data scan path to FL_DATA register. During this instruction, the length
of the scan chain is 18 bits. In the Capture-DR state, the Flash Read Data buffer and the two status bits are loaded into the
shift registers and the Valid bit is cleared. The Error bit indicates any error that occurred during the write operation.
If the Valid bit read was cleared, the data and error fields should be ignored. If the Valid status (RO) bit is cleared and the
Valid control bit is set (WO) during the Update-DR state, the data is loaded into the Flash Write Data buffer, starting the data
write sequence to the flash. When the write is completed, a flash read is performed, placing the data in the Flash Read Data
buffer. The data is then compared to the Flash Write Data buffer; if the two are different, the Program Error flag in the Control
Status register and the Error flags in the data register are set. The Valid bit read (RO) indicates when another word may be
written to the data write buffer.
When the flash address is in the flash main block or Information block, the data written is one word (16 bits) and the address
increment is two.
FMBUSY is set at the beginning (Update-DR) of the write process; it is cleared when the write to the flash is completed. The
Flash error flags are updated in case an error occurs during the write operation.
Flash Erase
The Flash Erase instruction switches the data scan path to FL_ERASE register. During this instruction, the length of the scan
chain is two bits. In the capture-DR state, the Flash Busy and Error bits are read. If the Busy bit is cleared, the Error bit
indicates any failure in the erase process.
During the Update-DR state of this instruction, the Start (WO) bit is loaded into the Control register. If the Start bit and any
of the Erase bits are set, the respective erase process starts. The Flash Address and Block ID are used to indicate the page
or sector to erase in the Page and Sector Erase commands, respectively.
When the erase is completed, the Busy bit is set. The Error flag indicates any failure that occurs in the flash erase procedure.
The FMBUSY and FMERR bits in Flash Status register are updated in parallel to the Erase instruction Busy and Error flags.
Debugger Interface Instructions
SCAN_RX
The SCAN_RX instruction switches the data scan path to DBGDATA register. The DBGDATA length is set to L0 to L4; see
“Debug Data Register (DBGDATA)” on page 261. The result of the Capture-DR state of the TAP controller is unpredictable.
A parallel load of data from DBGDATA register to the DBGRXD Rx data buffer is done in Update-DR state.
The controller sets the RX_BUSY indication in DBGRXST register to 1 in Update-DR state. The PID and message fields of
the SCAN_RX instruction are available for read access, through the peripheral bus, from DBGRXST register. The ISE inter-
rupt control block asserts the ISE interrupt and RX_i bit in DBGISESRC register, according to the PID index.
DEBUGGER ABORT
This operation has no dedicated operation code. It is performed using the SCAN_RX instruction with the PID field is ‘1111’.
Following SCAN_RX mode, the ISE interrupt control block asserts ISE interrupts, together with ABORT_i bits in
DBGISESRC register, according to the MASKS values in DBGMASKS register. The assertion is triggered during the TCK
rising edge during Update-IR state. In this case, there is no RX_BUSY indication and no change in the contents of DB-
GRXST register (i.e., this format of SCAN_RX may be issued with a busy Rx data link).
SCAN_TX
The SCAN_TX instruction switches the data scan path to DBGDATA register. In Capture-DR state, DBGDATA register cap-
tures the values from the Tx data buffer DBGTXD. No parallel load is performed in Update-DR state. The length of
DBGDATA register is set to the value of MSG_LEN in DBGTXST register (see “Debug Data Register (DBGDATA)” on
page 261). No parallel load is performed in Update-DR state.
The Controller sets DBGTXLOC to all 1s and releases TINT on Update-DR state. This operation clears the semaphore and
enables the data link for a new transaction. TINT is asserted, as described in “TX Data Link” on page 250.
Revision 1.07
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