pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 199

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Arbitration on the Bus
Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is
initially determined according to address bits and clock cycle. If more than one master tries to address the same slave, data
comparisons determine the outcome of this arbitration. In Master mode, the device immediately aborts a transaction if the
value sampled on the SDAn line differs from the value driven by the device. (An exception to this rule is SDAn while receiving
data; in this case, the lines may be driven low by the slave without causing an abort.)
The SCLn signal is monitored for clock synchronization to allow the slave to stall the bus. The actual clock period is the long-
est one set by the master or the slave stall period. The clock high period is determined by the master with the shortest clock
high period.
When an abort occurs during address transmission, a master that identifies the conflict should give up the bus and switch
to Slave mode. It should then continue to sample SDAn to see if it is being addressed by the winning master on the bus.
4.13.3 Master Mode
Requesting Bus Mastership
An ACCESS.bus transaction starts with a master device requesting bus mastership. It asserts a Start Condition, followed by
the address of the device it wants to access. If this transaction is successfully completed, the software may assume that the
device has become the bus master.
For the device to become the bus master, the software should perform the following steps:
1. Configure INTEN in ACBnCTL1 register to the desired operation mode (Polling or Interrupt) and set START in the same
2. If a bus conflict is detected (i.e., some other device pulls down the SCLn signal before the PC87591x does), BER in
3. If there is no bus conflict, MASTER and SDAST in ACBnST register are set.
4. If INTEN in ACBnCTL1 register is set and either BER or SDAST in ACBnST register is set, an interrupt is sent to the core.
Sending the Address Byte
Once the PC87591x is the active master of the ACCESS.bus (MASTER in ACBnST register is set), it can send the address
on the bus. The address sent should not be any of the following:
To send the address byte, use the following sequence:
1. For a receive transaction where the software requires only one byte of data, the software should set ACK in ACBnCTL1
2. Write the address byte (7-bit target device address) and the direction bit to ACBnSDA register. This causes the module
3. If STASTRE in ACBnCTL1 register is set and the transaction was successfully completed (i.e., both BER and NEGACK
4. If the requested direction is transmit and the start transaction was completed successfully (i.e., neither NEGACK nor BER
5. If the requested direction is receive, the start transaction was completed successfully and STASTRE in ACBnCTL1 reg-
6. Check that both BER and NEGACK in ACBnST register are cleared. If INTEN in ACBnCTL1 register is set, an interrupt
register. This causes the ACB to issue a Start Condition on the ACCESS.bus as soon as the ACCESS.bus is free (some
conditions, such as when BB in ACBnCST register is set to 0, can delay start). It then stalls the bus by holding SCLn low.
ACBnST register is set.
The PC87591x’s own address, as defined by ADDR in ACBnADDR register, if SAEN in ACBnADDR is set.
The PC87591x’s own address, as defined by ADDR in ACBnADDR2, if SAEN in ACBnADDR2 is set.
The global call address, if GCMTCH in ACBnST register is set.
The ARP address, if ARPMATCH in ACBnST register is set.
register. If only an address needs to be sent (e.g., for quick read/write protocols) or if the device requires stall for some
other reason, set STASTRE in ACBnCTL1 register to 1.
to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to NEGACK in ACBnST
register. During the transaction, the SDAn and SCLn lines are continuously checked for conflict with other devices. If a
conflict is detected, the transaction is aborted, BER in ACBnST register is set and MASTER in ACBnST register is
cleared.
in ACBnST register are cleared), STASTR in ACBnST register is set. In this case, the ACB stalls any further AC-
CESS.bus operations (i.e., holds SCLn low). If INTEN in ACBnCTL1 register is set, it also sends an interrupt to the core.
in ACBnST register is set and no other master has accessed the device), SDAST in ACBnST register is set to indicate
that the module awaits attention.
ister is cleared, the module starts receiving the first byte automatically.
is generated when either BER or NEGACK is set.
(Continued)
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