pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 230

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
Flash Memory Control Register (FLCR)
This register controls the on-chip flash operation modes. It is cleared (00
when HLOCK bit in SMCCST register is 0 (see Section 5.3.9 on page 307). Otherwise, writes are ignored.
Location: 00 F8C0
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
15-9 Reserved.
3-1
Bit
0
4
5
6
7
8
LOWPWR (Low Power Mode).
0: On-chip flash is in Normal mode
1: On-chip flash is in Low Power mode
This bit may be set (1) only when the core domain’s clock is up to f
It may be altered only when FRE bit in SZCFG1 register is set (1).
Reserved.
IENPROG (Interrupt Enable for Program).
0: Interrupt request disabled.
1: An interrupt request to the ICU is enabled (see FMLFULL in the Flash Memory Status register).
PE (Program Enable). This bit is impact core program operations only.
0: Flash Programing is disabled (default)
1: Flash Programing is enabled (if PMER and SMER are cleared)
PMER (Page Erase). When set (1) a valid write to the on-chip flash erases the entire page pointed to by the
write address. This bit affects core erase operations only.
This bit may be modified, only when the FMBUSY bit is cleared (0); otherwise, results are undefined.
0: Flash Page Erase is disabled (default)
1: Flash Page Erase is enabled (if PE and SMER are cleared).
SMER (Section Erase). When set (1), a valid write to the on-chip flash erases the entire section pointed to by
the write address.
Write to a Main Block address results in a Main Block section erase.
Write to an Information Block address results in an Information Block section and its corresponding Main Block
section erase. This bit affects core erase operations only.
This bit may be modified only when the FMBUSY bit is cleared (0); otherwise, results are undefined.
0: Flash Section Erase is disabled (default)
1: Flash Section Erase is enabled (if PMER and PE are cleared).
DISVRF (Disable Verify). This bit affects core program and erase operations only.
0: Verify flash contents after program or erase is enabled (default).
1: Disable the automatic verification of flash contents after program or erase.
This speeds up the program or erase speed.
SMER
16
15
7
0
0
PMER
14
6
0
0
(Continued)
PE
13
5
0
0
IENPROG
Reserved
Description
230
12
4
0
0
16
11
3
0
0
) on reset. The core can write this register only
FLPMAX
Reserved
.
10
2
0
0
1
0
9
0
LOWPWR
DISVRF
Revision 1.07
0
0
8
0