pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 165

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Pre-Scale
A pre-scale counter divides the input clock (32.768 KHz) by a factor of 2
through 5 (i.e., divide ratio of 1:1 through 1:32). The pre-scaled output is used as an input clock for a 16-bit timer (TWDT0)
and is referred to as T0IN.
TWD Timer 0
TWD Timer 0 is a 16-bit, programmable, automatically re-triggered down-counter. It counts on the rising edge of T0IN. It starts
from the value loaded to TWDT0 register down to zero and then restarts counting from TWDT0 at the next T0IN cycle.
When the counter reaches 0, T0OUT is set (1) for one T0IN cycle. This makes the Timer 0 cycle:
T0OUT is input to the ICU and can be used as the time base for activities such as system tick.
When TWDT0 is loaded with a new value, the counter uses it the next time it restarts counting (i.e., after reaching zero). If
RST in Timer Control register (T0CSR) is written 1, the timer is restarted on the next rising edge of T0IN.
Notes:
WATCHDOG Operation
The WATCHDOG is an 8-bit down counter, operating on the rising edge of its currently selected clock source. On reset, it
is disabled (i.e., it does not count and no WATCHDOG signal is generated). A write to the WATCHDOG Count register
(WDCNT) or the WATCHDOG Service Data Match (WDSDM) register either starts the counter or, if WATCHDOG is already
running, performs a restart (“touch”) operation. Once the WATCHDOG is counting down, only a reset can stop it.
Writing to WDCNT register is enabled while LWDCNT in TWCFG register is 0. A write to WDCNT starts the WATCHDOG,
and it begins counting down from the written value. If the service on data match is enabled (WDSDME in TWCFG register
is 1), writing to WDSDM register with 5C
A WATCHDOG signal is triggered if one of the following occurs:
WATCHDOG Clock Source Selection
Select the clock source as follows:
Changing the WATCHDOG clock source may cause it to gain or lose one clock cycle.
Notes:
TWD Control and Configuration
The TWD Configuration register (TWCFG) allows you to:
Once LTWCFG, LTWCP, LTWDT0 or LWDCNT, in TWCFG register, is set its respective resources are locked and can be
cleared only by reset. Setting any of these registers prevents runaway software from tampering with the respective WATCH-
DOG function.
Operation in Idle Mode
The TWD is active in Idle mode: the counters continue to function, and interrupts and error signals are issued.
Write operations to TWCP, TWDT0 and WDCNT may be delayed by up to three 32.768 KHz clock cycles. The software should
avoid entering Idle mode during this period. WDTLD bit in T0CSR register indicates when it is safe to switch power modes.
RST bit in T0CSR register is cleared after completing this load.
When MDIV in TWCP register is 0, the timer counter may skip one count when loaded with a new value.
The counter reaches zero (too late service).
The WATCHDOG is written to more than once per WATCHDOG clock cycle for the currently selected clock (too early
service). Writing to the WATCHDOG more than once per three WATCHDOG clock cycles (for the currently selected
clock) may cause the WATCHDOG signal to trigger.
Data other than 5C
WDCT01 bit in TWCFG register is 0:
WDCT01 bit in TWCFG register is 1:
When MDIV in TWCP register is 0, the WATCHDOG counter may skip one count when loaded with a new value.
After activating WATCHDOG, avoid entering Idle mode in the first four low-frequency clock cycles.
Set the WATCHDOG clock source: T0IN or T0OUT
Enable WATCHDOG service on write to WDSDM register
Define which of TWCFG, TWCPR, TWDT0, T0CSR and WDCNT is locked.
(TWDT0 + 1) x T0IN-cycle.
16
is written to WDSDM when WDSDME in TWCFG register is 1.
16
restarts the WATCHDOG counter from the value stored in WDCNT.
(Continued)
T0OUT
T0IN
165
MDIV
. MDIV in TWCP register is in the range of 0
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