pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 205

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
ACB Control Register 1 (ACBnCTL1)
The ACBnCTL1 register is a byte-wide, read/write register that configures and controls the ACB module. On reset, the
ACBnCTL1 is cleared (00
Location: Channel 1 - 00 FF66
Type: R/W
Bit
Name
Reset
Bit
0
1
2
3
4
5
6
7
START. Should be set when a Start Condition must be generated on the ACCESS.bus.
– If the PC87591x is not the active bus master (MASTER in ACBnST register is set to 0), setting START gener-
– If the PC87591x is the active master of the bus (MASTER in ACBnST register is set to 1), when START is set,
The START bit is cleared either when the Start Condition is sent or on detection of a Bus Error (BER in ACBnST
register is set to 1).
This bit should be set only when in Master mode or when requesting Master mode.
STOP. In Master mode, setting this bit generates a Stop Condition, which completes or aborts the current
message transfer. This bit clears itself after STOP is issued.
INTEN (Interrupt Enable). When INTEN is cleared (0), the ACB interrupt is disabled. When INTEN is set,
interrupts are enabled. An interrupt is generated (the interrupt signals to the ICU are high) on one of the
following events:
– An address match is detected (NMATCH in ACBnST register is set to1 and NMINTE in ACBnCTL1 register is
– A Bus Error occurs (BER in ACBnST register is set to 1).
– A negative acknowledge is received after sending a byte (NEGACK in ACBnST register is set to 1).
– Acknowledgment of each transaction (same as the hardware set of SDAST in ACBnST).
– In Master mode, if STASTRE in ACBnCTL1 register is set to 1 after a successful start (STASTR in ACBnST
– Detection of a Stop Condition while in Slave mode (SLVSTP in ACBnST register is set to 1).
Reserved.
ACK (Acknowledge). When acting as a receiver, this bit holds the value of the next acknowledge cycle. It
should be set when a negative acknowledge must be issued on the next byte. This bit is cleared (0) after the
first acknowledge cycle.
This bit is ignored when in Transmit mode. It cannot be reset by software.
GCMEN (Global Call Match Enable). When set, enables the matching of an incoming address byte to the
general call address (Start Condition followed by address byte of 00
cleared, the ACB does not respond to a global call.
NMINTE (New Match Interrupt Enable). When set, enables the interrupt on a new match (i.e., when NMATCH
in ACBnST register is set). The interrupt is issued only if INTEN in ACBnCTL1 register is set.
STASTRE (Stall After Start Enable). When set (1), enables the Stall After Start mechanism. In such a case,
the ACB stalls the bus after the address byte. When STASTRE is cleared, STASTR in ACBnST is always
cleared.
Channel 2 - 00 FFE6
ates a Start Condition as soon as the ACCESS.bus is free (BB in ACBnCST register is set to 0). An address
transmission sequence should then be performed.
a write to ACBnSDA register generates a Start Condition. ACBnSDA data is then transmitted as the slave’s ad-
dress and the requested transfer direction.
In case of a Repeated Start Condition, the set bit may be used to switch the direction of the data flow between
the master and the slave or to choose another slave device without using a Stop Condition in between.
set to 1).
register is set to 1).
STASTRE
7
0
16
).
NMINTE
16
16
6
0
GCMEN
(Continued)
5
0
ACK
Description
205
4
0
Reserved
3
0
16
) while the ACB is in Slave mode. When
INTEN
0
2
STOP
1
0
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START
0
0