pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 198

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
“Acknowledge After Every Byte” Rule
The master generates an Acknowledge clock pulse after each byte transfer. The receiver sends an Acknowledge signal after
every byte is received.
There are two exceptions to the “acknowledge after every byte” rule:
Addressing Transfer Formats
Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave
being addressed. The slave device should send an Acknowledge signal on the SDAn line once it recognizes its address.
The address consists of the first seven bits after a Start Condition. The eighth bit contains the direction of the data transfer
(R/W). A low-to-high transition during a SCLn high period indicates the Stop Condition and ends the transaction of SDAn
(Figure 73).
When the address is sent, each device in the system compares this address with its own. If there is a match, the device
considers itself addressed and sends an Acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the
device acts as a transmitter or a receiver.
The I
the general call address (00
software only”). Slaves that require data acknowledge the call and become slave receivers; other slaves ignore the call.
When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative
acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the Acknowledge clock
pulse (generated by the master), but the SDAn line is not pulled down.
When the receiver is full or otherwise occupied, or if a problem occurs, it sends a negative acknowledge to indicate
that it cannot accept additional data bytes.
2
C bus protocol allows a general call address to be sent to all slaves connected to the bus. The first byte sent specifies
Data Output
Receiver
Transmitter
Data Output
SDAn
SCLn
SCLn
Start
Condition
16
S
); the second byte specifies the general call meaning (for example, “Write slave address by
Figure 73. A Complete ACCESS.bus Data Transaction
Start
Condition
S
Address R/W ACK
1 - 7
Figure 72. ACCESS.bus Acknowledge Cycle
1
(Continued)
8
2 3 - 6
9
7
1 - 7
Data
198
8
9
8
ACK
9
1 - 7
Data
Transmitter Stays Off the
Bus During the
Acknowledge Clock
Acknowledge
Signal from Receiver
8
ACK
9
Stop
Condition
P
Revision 1.07