pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 75

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
4.0 Embedded Controller Modules
At the first TIW or T2 (when there are no TIW cycles), the data is placed on the data bus. The bus cycle is completed at T2;
at this point, WR0-1 are deactivated. The address and data remain valid until T2 is completed.
After T2, the number of T
T
on the first T
another read or write from the same zone follows. The data is put in TRI-STATE in the clock cycle after the last T
(if no T
hold
Data placed
on D0-15
cycles are added, the address and data remain valid until the end of the last T
Hold cycles
according to
HOLD in
SZCFGn reg.
hold
First T
SELn: inactive.
TIW
Note: References to SZCFGn also apply to the IOCFG register.
cycle is configured); see Figures 15, 16 and 17.
HOLD field in SZCFGn reg.
WAIT field in SZCFGn reg.
hold
hold
cycle. When no T
References to SELn also apply to the SELIO signal.
;
Internal waits completed
Hold cycles completed
Internal waits corresponding to WAIT field in SZCFGn register
hold
T
cycles specified by HOLD in SZCFGn register (may be 0) is added to the transaction. When
hold
hold
cycles are specified, SELn (or SELIO) is deactivated in the clock cycle after T2 unless
0
0
Figure 15. Late Write Bus Cycle
(Continued)
begin
end
T2
T1
HOLD field in SZCFGn reg. = 0
75
Address placed on A0-19;
SELn: activated;
WR0-1: activated.
Data placed on D0-15;
WR0-1: inactive.
Address on A0-19 invalid/changed;
Data put in TRI-STATE;
SELn: inactive.
hold
cycle. SELn (or SELIO) is deactivated
WAIT field in SZCFGn reg. = 0
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hold
or T2